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x86/suspend: Simplify system table handling on resume
load_TR() is used exclusively in the resume path, but jumps through a lot of unnecessary hoops. As suspend/resume is strictly on CPU0 in idle context, the correct GDT to use is boot_gdt, which means it doesn't need saving on suspend. Although doing more than strictly necessary, reuse load_system_tables(), which is already used by APs on the S3 resume path. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Jan Beulich <jbeulich@suse.com>
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08baf55f33
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4 files changed
+2
-36
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@@ -41,7 +41,7 @@ void save_rest_processor_state(void)
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void restore_rest_processor_state(void)
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{
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load_TR();
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load_system_tables();
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/* Recover syscall MSRs */
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wrmsrl(MSR_LSTAR, saved_lstar);
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@@ -34,10 +34,6 @@ ENTRY(do_suspend_lowlevel)
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mov %ss, REF(saved_ss)
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sgdt REF(saved_gdt)
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sidt REF(saved_idt)
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sldt REF(saved_ldt)
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mov %cr0, GREG(ax)
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mov GREG(ax), REF(saved_cr0)
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@@ -55,6 +51,7 @@ ENTRY(do_suspend_lowlevel)
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ENTRY(__ret_point)
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lgdt boot_gdtr(%rip)
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/* mmu_cr4_features contains latest cr4 setting */
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mov REF(mmu_cr4_features), GREG(ax)
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@@ -66,10 +63,6 @@ ENTRY(__ret_point)
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mov REF(saved_cr0), GREG(ax)
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mov GREG(ax), %cr0
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lgdt REF(saved_gdt)
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lidt REF(saved_idt)
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lldt REF(saved_ldt)
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mov REF(saved_ss), %ss
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LOAD_GREG(sp)
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@@ -129,9 +122,5 @@ DECLARE_GREG(13)
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DECLARE_GREG(14)
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DECLARE_GREG(15)
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saved_gdt: .quad 0,0
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saved_idt: .quad 0,0
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saved_ldt: .quad 0,0
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saved_cr0: .quad 0
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saved_cr3: .quad 0
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@@ -1887,27 +1887,6 @@ static void __init set_intr_gate(unsigned int n, void *addr)
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__set_intr_gate(n, 0, addr);
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}
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void load_TR(void)
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{
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struct tss64 *tss = &this_cpu(tss_page).tss;
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struct desc_ptr old_gdt, tss_gdt = {
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.base = (long)(this_cpu(gdt) - FIRST_RESERVED_GDT_ENTRY),
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.limit = LAST_RESERVED_GDT_BYTE
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};
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_set_tssldt_desc(
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this_cpu(gdt) + TSS_ENTRY - FIRST_RESERVED_GDT_ENTRY,
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(unsigned long)tss, sizeof(*tss) - 1, SYS_DESC_tss_avail);
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_set_tssldt_desc(
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this_cpu(compat_gdt) + TSS_ENTRY - FIRST_RESERVED_GDT_ENTRY,
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(unsigned long)tss, sizeof(*tss) - 1, SYS_DESC_tss_busy);
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/* Switch to non-compat GDT (which has B bit clear) to execute LTR. */
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asm volatile (
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"sgdt %0; lgdt %2; ltr %w1; lgdt %0"
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: "=m" (old_gdt) : "rm" (TSS_SELECTOR), "m" (tss_gdt) : "memory" );
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}
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static unsigned int calc_ler_msr(void)
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{
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switch ( boot_cpu_data.x86_vendor )
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@@ -216,8 +216,6 @@ DECLARE_PER_CPU(seg_desc_t *, compat_gdt);
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DECLARE_PER_CPU(l1_pgentry_t, compat_gdt_l1e);
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DECLARE_PER_CPU(bool, full_gdt_loaded);
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extern void load_TR(void);
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static inline void lgdt(const struct desc_ptr *gdtr)
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{
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__asm__ __volatile__ ( "lgdt %0" :: "m" (*gdtr) : "memory" );
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