x86/PV: make PMU MSR handling consistent

So far accesses to Intel MSRs on an AMD system fall through to the
default case, while accesses to AMD MSRs on an Intel system bail (in
the RDMSR case without updating EAX and EDX). Make the "AMD MSRs on
Intel" case match the "Intel MSR on AMD" one.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

xen/arch/x86/traps.c

@@ -2912,8 +2912,8 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
 
                     if ( vpmu_do_wrmsr(regs->ecx, msr_content, 0) )
                         goto fail;
+                    break;
                 }
-                break;
             }
             /*FALLTHROUGH*/
 
@@ -3048,8 +3048,8 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
 
                     regs->eax = (uint32_t)val;
                     regs->edx = (uint32_t)(val >> 32);
+                    break;
                 }
-                break;
             }
             /*FALLTHROUGH*/