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mini-os/x86-64 entry: code refactoring; no functional changes
Re-arrange assembly code blocks so that they are in called order instead of jumping around, enhancing readability. Macros are grouped together as well. Signed-off-by: Xu Zhang <xzhang@cs.uic.edu> Acked-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
This commit is contained in:
Xu Zhang authored and Ian Campbell committed
1 parent
7e84f54da5
commit
bf65a5d69b
1 file changed
+57
-56
@@ -36,6 +36,22 @@ hypercall_page:
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.org 0x3000
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#define XEN_GET_VCPU_INFO(reg) movq HYPERVISOR_shared_info,reg
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#define XEN_PUT_VCPU_INFO(reg)
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#define XEN_PUT_VCPU_INFO_fixup
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#define XEN_LOCKED_BLOCK_EVENTS(reg) movb $1,evtchn_upcall_mask(reg)
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#define XEN_LOCKED_UNBLOCK_EVENTS(reg) movb $0,evtchn_upcall_mask(reg)
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#define XEN_TEST_PENDING(reg) testb $0xFF,evtchn_upcall_pending(reg)
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#define XEN_BLOCK_EVENTS(reg) XEN_GET_VCPU_INFO(reg) ; \
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XEN_LOCKED_BLOCK_EVENTS(reg) ; \
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XEN_PUT_VCPU_INFO(reg)
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#define XEN_UNBLOCK_EVENTS(reg) XEN_GET_VCPU_INFO(reg) ; \
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XEN_LOCKED_UNBLOCK_EVENTS(reg) ; \
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XEN_PUT_VCPU_INFO(reg)
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/* Offsets into shared_info_t. */
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#define evtchn_upcall_pending /* 0 */
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#define evtchn_upcall_mask 1
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@@ -46,6 +62,27 @@ NMI_MASK = 0x80000000
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#define ORIG_RAX 120 /* + error_code */
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#define EFLAGS 144
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/* Macros */
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.macro zeroentry sym
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movq (%rsp),%rcx
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movq 8(%rsp),%r11
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addq $0x10,%rsp /* skip rcx and r11 */
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pushq $0 /* push error code/oldrax */
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pushq %rax /* push real oldrax to the rdi slot */
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leaq \sym(%rip),%rax
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jmp error_entry
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.endm
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.macro errorentry sym
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movq (%rsp),%rcx
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movq 8(%rsp),%r11
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addq $0x10,%rsp /* rsp points to the error code */
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pushq %rax
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leaq \sym(%rip),%rax
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jmp error_entry
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.endm
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.macro RESTORE_ALL
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movq (%rsp),%r11
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movq 1*8(%rsp),%r10
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@@ -130,42 +167,10 @@ error_call_handler:
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call *%rax
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jmp error_exit
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.macro zeroentry sym
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movq (%rsp),%rcx
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movq 8(%rsp),%r11
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addq $0x10,%rsp /* skip rcx and r11 */
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pushq $0 /* push error code/oldrax */
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pushq %rax /* push real oldrax to the rdi slot */
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leaq \sym(%rip),%rax
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jmp error_entry
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.endm
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.macro errorentry sym
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movq (%rsp),%rcx
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movq 8(%rsp),%r11
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addq $0x10,%rsp /* rsp points to the error code */
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pushq %rax
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leaq \sym(%rip),%rax
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jmp error_entry
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.endm
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#define XEN_GET_VCPU_INFO(reg) movq HYPERVISOR_shared_info,reg
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#define XEN_PUT_VCPU_INFO(reg)
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#define XEN_PUT_VCPU_INFO_fixup
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#define XEN_LOCKED_BLOCK_EVENTS(reg) movb $1,evtchn_upcall_mask(reg)
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#define XEN_LOCKED_UNBLOCK_EVENTS(reg) movb $0,evtchn_upcall_mask(reg)
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#define XEN_TEST_PENDING(reg) testb $0xFF,evtchn_upcall_pending(reg)
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#define XEN_BLOCK_EVENTS(reg) XEN_GET_VCPU_INFO(reg) ; \
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XEN_LOCKED_BLOCK_EVENTS(reg) ; \
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XEN_PUT_VCPU_INFO(reg)
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#define XEN_UNBLOCK_EVENTS(reg) XEN_GET_VCPU_INFO(reg) ; \
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XEN_LOCKED_UNBLOCK_EVENTS(reg) ; \
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XEN_PUT_VCPU_INFO(reg)
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/*
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* Xen event (virtual interrupt) entry point.
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*/
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ENTRY(hypervisor_callback)
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zeroentry hypervisor_callback2
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@@ -178,7 +183,23 @@ ENTRY(hypervisor_callback2)
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call do_hypervisor_callback
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popq %rsp
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decl %gs:0
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jmp error_exit
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error_exit:
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RESTORE_REST
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XEN_BLOCK_EVENTS(%rsi)
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retint_kernel:
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retint_restore_args:
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movl EFLAGS-6*8(%rsp), %eax
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shr $9, %eax # EAX[0] == IRET_EFLAGS.IF
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XEN_GET_VCPU_INFO(%rsi)
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andb evtchn_upcall_mask(%rsi),%al
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andb $1,%al # EAX[0] == IRET_EFLAGS.IF & event_mask
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jnz restore_all_enable_events # != 0 => enable event delivery
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XEN_PUT_VCPU_INFO(%rsi)
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RESTORE_ALL
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HYPERVISOR_IRET 0
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restore_all_enable_events:
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XEN_UNBLOCK_EVENTS(%rsi) # %rsi is already set up...
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@@ -198,26 +219,6 @@ scrit: /**** START OF CRITICAL REGION ****/
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ecrit: /**** END OF CRITICAL REGION ****/
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retint_kernel:
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retint_restore_args:
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movl EFLAGS-6*8(%rsp), %eax
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shr $9, %eax # EAX[0] == IRET_EFLAGS.IF
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XEN_GET_VCPU_INFO(%rsi)
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andb evtchn_upcall_mask(%rsi),%al
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andb $1,%al # EAX[0] == IRET_EFLAGS.IF & event_mask
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jnz restore_all_enable_events # != 0 => enable event delivery
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XEN_PUT_VCPU_INFO(%rsi)
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RESTORE_ALL
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HYPERVISOR_IRET 0
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error_exit:
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RESTORE_REST
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XEN_BLOCK_EVENTS(%rsi)
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jmp retint_kernel
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ENTRY(failsafe_callback)
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popq %rcx
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