Enable RDWRGSFS feature support for HVM guests

Write/read FS/GS base instructions enable user level code to
read/write FS & GS segment base registers for thread local storage.

Signed-off-by: Yang, Wei <wei.y.yang@intel.com>

tools/libxc/xc_cpuid_x86.c

@@ -356,7 +356,8 @@ static void xc_cpuid_hvm_policy(
     case 0x00000007: /* Intel-defined CPU features */
         if ( input[1] == 0 ) {
             regs[1] &= (bitmaskof(X86_FEATURE_SMEP) |
-                        bitmaskof(X86_FEATURE_ERMS));
+                        bitmaskof(X86_FEATURE_ERMS) |
+                        bitmaskof(X86_FEATURE_FSGSBASE));
         } else
             regs[1] = 0;
         regs[0] = regs[2] = regs[3] = 0;

xen/include/asm-x86/hvm/hvm.h

@@ -325,6 +325,7 @@ static inline int hvm_do_pmu_interrupt(struct cpu_user_regs *regs)
         X86_CR4_MCE | X86_CR4_PGE | X86_CR4_PCE |       \
         X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT |           \
         (cpu_has_smep ? X86_CR4_SMEP : 0) |             \
+        (cpu_has_fsgsbase ? X86_CR4_FSGSBASE : 0) |     \
         ((nestedhvm_enabled((_v)->domain) && cpu_has_vmx)\
                       ? X86_CR4_VMXE : 0)  |             \
         (xsave_enabled(_v) ? X86_CR4_OSXSAVE : 0))))