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xen/arm: refactor vpl011_data_avail
Move the code to calculate in_fifo_level and out_fifo_level out of vpl011_data_avail, to the caller. This change will make it possible to reuse vpl011_data_avail with different ring structures in a later patch. Signed-off-by: Stefano Stabellini <stefanos@xilinx.com> Acked-by: Julien Grall <julien.grall@arm.com>
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1 parent
c7d4847a43
commit
c71e06cc84
1 file changed
+56
-48
+56
-48
@@ -379,9 +379,62 @@ static const struct mmio_handler_ops vpl011_mmio_handler = {
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.write = vpl011_mmio_write,
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};
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static void vpl011_data_avail(struct domain *d)
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static void vpl011_data_avail(struct domain *d,
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XENCONS_RING_IDX in_fifo_level,
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XENCONS_RING_IDX in_size,
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XENCONS_RING_IDX out_fifo_level,
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XENCONS_RING_IDX out_size)
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{
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struct vpl011 *vpl011 = &d->arch.vpl011;
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/**** Update the UART RX state ****/
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/* Clear the FIFO_EMPTY bit if the FIFO holds at least one character. */
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if ( in_fifo_level > 0 )
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vpl011->uartfr &= ~RXFE;
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/* Set the FIFO_FULL bit if the Xen buffer is full. */
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if ( in_fifo_level == in_size )
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vpl011->uartfr |= RXFF;
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/* Assert the RX interrupt if the FIFO is more than half way filled. */
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if ( in_fifo_level >= in_size - SBSA_UART_FIFO_LEVEL )
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vpl011->uartris |= RXI;
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/*
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* If the input queue is not empty, we assert the receive timeout interrupt.
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* As we don't emulate any timing here, so we ignore the actual timeout
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* of 32 baud cycles.
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*/
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if ( in_fifo_level > 0 )
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vpl011->uartris |= RTI;
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/**** Update the UART TX state ****/
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if ( out_fifo_level != out_size )
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{
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vpl011->uartfr &= ~TXFF;
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/*
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* Clear the BUSY bit as soon as space becomes available
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* so that the SBSA UART driver can start writing more data
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* without any further delay.
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*/
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vpl011->uartfr &= ~BUSY;
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vpl011_update_tx_fifo_status(vpl011, out_fifo_level);
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}
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vpl011_update_interrupt_status(d);
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if ( out_fifo_level == 0 )
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vpl011->uartfr |= TXFE;
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}
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static void vpl011_notification(struct vcpu *v, unsigned int port)
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{
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unsigned long flags;
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struct domain *d = v->domain;
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struct vpl011 *vpl011 = &d->arch.vpl011;
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struct xencons_interface *intf = vpl011->backend.dom.ring_buf;
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XENCONS_RING_IDX in_cons, in_prod, out_cons, out_prod;
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@@ -404,57 +457,12 @@ static void vpl011_data_avail(struct domain *d)
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out_cons,
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sizeof(intf->out));
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/**** Update the UART RX state ****/
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/* Clear the FIFO_EMPTY bit if the FIFO holds at least one character. */
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if ( in_fifo_level > 0 )
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vpl011->uartfr &= ~RXFE;
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/* Set the FIFO_FULL bit if the Xen buffer is full. */
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if ( in_fifo_level == sizeof(intf->in) )
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vpl011->uartfr |= RXFF;
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/* Assert the RX interrupt if the FIFO is more than half way filled. */
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if ( in_fifo_level >= sizeof(intf->in) - SBSA_UART_FIFO_LEVEL )
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vpl011->uartris |= RXI;
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/*
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* If the input queue is not empty, we assert the receive timeout interrupt.
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* As we don't emulate any timing here, so we ignore the actual timeout
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* of 32 baud cycles.
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*/
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if ( in_fifo_level > 0 )
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vpl011->uartris |= RTI;
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/**** Update the UART TX state ****/
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if ( out_fifo_level != sizeof(intf->out) )
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{
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vpl011->uartfr &= ~TXFF;
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/*
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* Clear the BUSY bit as soon as space becomes available
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* so that the SBSA UART driver can start writing more data
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* without any further delay.
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*/
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vpl011->uartfr &= ~BUSY;
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vpl011_update_tx_fifo_status(vpl011, out_fifo_level);
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}
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vpl011_update_interrupt_status(d);
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if ( out_fifo_level == 0 )
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vpl011->uartfr |= TXFE;
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vpl011_data_avail(v->domain, in_fifo_level, sizeof(intf->in),
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out_fifo_level, sizeof(intf->out));
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VPL011_UNLOCK(d, flags);
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}
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static void vpl011_notification(struct vcpu *v, unsigned int port)
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{
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vpl011_data_avail(v->domain);
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}
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int domain_vpl011_init(struct domain *d, struct vpl011_init_info *info)
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{
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int rc;
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