bitkeeper revision 1.1159.183.1 (41a0fd5c_SO-Z8P4u52CN53Q0eDzqg)

Clean up cacheline-alignment attribute usage. Also add an extra byte to the
TSS I/O bitmap as required by the arch manual.

xen/arch/x86/idle0_task.c

@@ -14,11 +14,4 @@
 
 struct domain idle0_task = IDLE0_TASK(idle0_task);
 
-/*
- * per-CPU TSS segments. Threads are completely 'soft' on Linux,
- * no more per-task TSS's. The TSS size is kept cacheline-aligned
- * so they are allowed to end up in the .data.cacheline_aligned
- * section. Since TSS's are completely CPU-local, we want them
- * on exact cacheline boundaries, to eliminate cacheline ping-pong.
- */ 
-struct tss_struct init_tss[NR_CPUS] __cacheline_aligned;
+struct tss_struct init_tss[NR_CPUS];

xen/arch/x86/irq.c

@@ -13,7 +13,7 @@
 #include <xen/sched.h>
 #include <asm/smpboot.h>
 
-irq_desc_t irq_desc[NR_IRQS] __cacheline_aligned;
+irq_desc_t irq_desc[NR_IRQS];
 
 static void __do_IRQ_guest(int irq);
 

xen/arch/x86/memory.c

@@ -130,7 +130,7 @@ static struct {
     unsigned long       cr0;
     /* If non-NULL, specifies a foreign subject domain for some operations. */
     struct domain      *foreign;
-} percpu_info[NR_CPUS] __cacheline_aligned;
+} __cacheline_aligned percpu_info[NR_CPUS];
 
 /*
  * Returns the current foreign domain; defaults to the currently-executing

xen/arch/x86/smpboot.c

@@ -67,7 +67,7 @@ static volatile unsigned long cpu_callin_map;
 static volatile unsigned long cpu_callout_map;
 
 /* Per CPU bogomips and other parameters */
-struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
+struct cpuinfo_x86 cpu_data[NR_CPUS];
 
 /* Set when the idlers are all forked */
 int smp_threads_ready;

xen/arch/x86/traps.c

@@ -713,7 +713,11 @@ __asm__ __volatile__ ("movw %w3,0(%2)\n\t" \
 
 void set_tss_desc(unsigned int n, void *addr)
 {
-    _set_tssldt_desc(gdt_table+__TSS(n), (int)addr, 8299, 0x89);
+    _set_tssldt_desc(
+        gdt_table + __TSS(n),
+        (int)addr,
+        offsetof(struct tss_struct, __cacheline_filler) - 1,
+        0x89);
 }
 
 void __init trap_init(void)

xen/arch/x86/x86_32/xen.lds

@@ -65,9 +65,6 @@ SECTIONS
   . = ALIGN(4096);
   .data.page_aligned : { *(.data.idt) } :text
 
-  . = ALIGN(32);
-  .data.cacheline_aligned : { *(.data.cacheline_aligned) } :text
-
   __bss_start = .;		/* BSS */
   .bss : {
 	*(.bss)

xen/arch/x86/x86_64/xen.lds

@@ -63,9 +63,6 @@ SECTIONS
   . = ALIGN(4096);
   .data.page_aligned : { *(.data.idt) } :text
 
-  . = ALIGN(32);
-  .data.cacheline_aligned : { *(.data.cacheline_aligned) } :text
-
   __bss_start = .;		/* BSS */
   .bss : {
 	*(.bss)

xen/common/domain.c

@@ -18,7 +18,7 @@
 #include <asm/domain_page.h>
 
 /* Both these structures are protected by the domlist_lock. */
-rwlock_t domlist_lock __cacheline_aligned = RW_LOCK_UNLOCKED;
+rwlock_t domlist_lock = RW_LOCK_UNLOCKED;
 struct domain *domain_hash[DOMAIN_HASH_SIZE];
 struct domain *domain_list;
 

xen/common/softirq.c

@@ -17,7 +17,7 @@
 
 irq_cpustat_t irq_stat[NR_CPUS];
 
-static softirq_handler softirq_handlers[NR_SOFTIRQS] __cacheline_aligned;
+static softirq_handler softirq_handlers[NR_SOFTIRQS];
 
 asmlinkage void do_softirq()
 {

xen/include/asm-x86/config.h

@@ -55,8 +55,6 @@
  */
 #define SMP_CACHE_BYTES 64
 #define NR_CPUS 16
-#define __cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
-#define ____cacheline_aligned __cacheline_aligned
 
 /* Linkage for x86 */
 #define asmlinkage        __attribute__((regparm(0)))

xen/include/asm-x86/hardirq.h

@@ -4,13 +4,12 @@
 #include <xen/config.h>
 #include <xen/cache.h>
 
-/* assembly code in softirq.h is sensitive to the offsets of these fields */
 typedef struct {
 	unsigned int __softirq_pending;
 	unsigned int __local_irq_count;
 	unsigned int __nmi_count;
 	unsigned long idle_timestamp;
-} ____cacheline_aligned irq_cpustat_t;
+} __cacheline_aligned irq_cpustat_t;
 
 #include <xen/irq_cpustat.h>	/* Standard mappings for irq_cpustat_t above */
 

xen/include/asm-x86/pda.h

@@ -14,7 +14,7 @@ struct x8664_pda {
 	int cpunumber;		    /* Logical CPU number */
 	char *irqstackptr;	/* top of irqstack */
 	unsigned long volatile *level4_pgt; 
-} ____cacheline_aligned;
+} __cacheline_aligned;
 
 #define PDA_STACKOFFSET (5*8)
 

xen/include/asm-x86/processor.h

@@ -280,7 +280,7 @@ static inline void clear_in_cr4 (unsigned long mask)
 #define IOBMP_BYTES             8192
 #define IOBMP_BYTES_PER_SELBIT  (IOBMP_BYTES / 64)
 #define IOBMP_BITS_PER_SELBIT   (IOBMP_BYTES_PER_SELBIT * 8)
-#define IOBMP_OFFSET            offsetof(struct tss_struct,io_bitmap)
+#define IOBMP_OFFSET            offsetof(struct tss_struct, io_bitmap)
 #define IOBMP_INVALID_OFFSET    0x8000
 
 struct i387_state {
@@ -322,9 +322,9 @@ struct tss_struct {
     u16 trace;
 #endif
     u16 bitmap;
-    u8  io_bitmap[IOBMP_BYTES];
+    u8  io_bitmap[IOBMP_BYTES+1];
     /* Pads the TSS to be cacheline-aligned (total size is 0x2080). */
-    u32 __cacheline_filler[6];
+    u8 __cacheline_filler[23];
 };
 
 struct trap_bounce {

xen/include/asm-x86/x86_32/uaccess.h

@@ -23,7 +23,7 @@
 #ifdef CONFIG_X86_INTEL_USERCOPY
 extern struct movsl_mask {
 	int mask;
-} ____cacheline_aligned_in_smp movsl_mask;
+} __cacheline_aligned movsl_mask;
 #endif
 
 #define __addr_ok(addr) ((unsigned long)(addr) < HYPERVISOR_VIRT_START)

xen/include/asm-x86/x86_64/desc.h

@@ -82,7 +82,7 @@ union desc_union {
 struct per_cpu_gdt {
 	struct ldttss_desc tss;
 	struct ldttss_desc ldt; 
-} ____cacheline_aligned; 
+} __cacheline_aligned; 
 
 
 struct Xgt_desc_struct {

xen/include/xen/cache.h

@@ -12,26 +12,8 @@
 #define SMP_CACHE_BYTES L1_CACHE_BYTES
 #endif
 
-#ifndef ____cacheline_aligned
-#define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
-#endif
-
-#ifndef ____cacheline_aligned_in_smp
-#ifdef CONFIG_SMP
-#define ____cacheline_aligned_in_smp ____cacheline_aligned
-#else
-#define ____cacheline_aligned_in_smp
-#endif /* CONFIG_SMP */
-#endif
-
 #ifndef __cacheline_aligned
-#ifdef MODULE
-#define __cacheline_aligned ____cacheline_aligned
-#else
-#define __cacheline_aligned					\
-  __attribute__((__aligned__(SMP_CACHE_BYTES),			\
-		 __section__(".data.cacheline_aligned")))
+#define __cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
 #endif
-#endif /* __cacheline_aligned */
 
 #endif /* __LINUX_CACHE_H */

xen/include/xen/irq.h

@@ -54,7 +54,7 @@ typedef struct {
     struct irqaction *action;	/* IRQ action list */
     unsigned int depth;		/* nested irq disables */
     spinlock_t lock;
-} ____cacheline_aligned irq_desc_t;
+} __cacheline_aligned irq_desc_t;
 
 extern irq_desc_t irq_desc[NR_IRQS];
 

xen/include/xen/sched.h

@@ -6,6 +6,7 @@
 #include <xen/config.h>
 #include <xen/types.h>
 #include <xen/spinlock.h>
+#include <xen/cache.h>
 #include <asm/regs.h>
 #include <xen/smp.h>
 #include <asm/page.h>