x86, intel: Clear Error counter field when set new cmci owner

Since cmci might happened when cpu is taking down (cpu hotplug) before
setting new cmci owner while old owner is down. We need to clear the
corrected error counter field to make sure CMCI could be triggered on
the new owner.

Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Signed-off-by: Liping Ke <liping.ke@intel.com>

xen/arch/x86/cpu/mcheck/mce_intel.c

@@ -358,6 +358,12 @@ static int do_cmci_discover(int i)
         return 0;
     }
     set_bit(i, __get_cpu_var(mce_banks_owned));
+    /* Clear Corected Error Counter field, make sure CMCI could 
+     * be triggered on the new owner
+     */
+    msr = MSR_IA32_MC0_STATUS + 4 * i;
+    rdmsrl(msr, val);
+    wrmsrl(msr, val & ~MCi_STATUS_ERRCOUNT);
 out:
     clear_bit(i, __get_cpu_var(no_cmci_banks));
     return 1;

xen/arch/x86/cpu/mcheck/x86_mca.h

@@ -46,6 +46,8 @@
 #define MCi_STATUS_MSEC         0x00000000ffff0000ULL
 /* Other information */
 #define MCi_STATUS_OTHER        0x01ffffff00000000ULL
+/*Corrected Error Count*/
+#define MCi_STATUS_ERRCOUNT     0x001FFFC0000000000ULL 
 /* processor context corrupt */
 #define MCi_STATUS_PCC          0x0200000000000000ULL
 /* MSR_K8_MCi_ADDR register valid */