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x86: FRED enumerations
Of note, CR4.FRED is bit 32 and cannot enabled outside of 64bit mode. Most supported toolchains don't understand the FRED instructions yet. Nevertheless, ERETU and ERETS are easy to wrap (they encoded as REPZ/REPNE CLAC), while LKGS turns out not to be needed by Xen. We will need some alternatives based on FRED, so add a synthetic X86_FEATURE_XEN_FRED. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Jan Beulich <jbeulich@suse.com>
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@@ -4,6 +4,14 @@
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.byte 0x0f, 0x01, 0xfc
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.endm
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/* binutils >= 2.41 or LLVM >= 19 */
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.macro eretu
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.byte 0xf3, 0x0f, 0x01, 0xca
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.endm
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.macro erets
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.byte 0xf2, 0x0f, 0x01, 0xca
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.endm
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/*
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* Call a noreturn function. This could be JMP, but CALL results in a more
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* helpful backtrace. BUG is to catch functions which do decide to return...
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@@ -246,6 +246,9 @@ static inline bool boot_cpu_has(unsigned int feat)
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#define cpu_has_avx_vnni boot_cpu_has(X86_FEATURE_AVX_VNNI)
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#define cpu_has_avx512_bf16 boot_cpu_has(X86_FEATURE_AVX512_BF16)
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#define cpu_has_cmpccxadd boot_cpu_has(X86_FEATURE_CMPCCXADD)
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#define cpu_has_fred boot_cpu_has(X86_FEATURE_FRED)
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#define cpu_has_lkgs boot_cpu_has(X86_FEATURE_LKGS)
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#define cpu_has_nmi_src boot_cpu_has(X86_FEATURE_NMI_SRC)
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#define cpu_has_avx_ifma boot_cpu_has(X86_FEATURE_AVX_IFMA)
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/* CPUID level 0x80000021.eax */
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@@ -18,7 +18,7 @@ XEN_CPUFEATURE(ARCH_PERFMON, X86_SYNTH( 3)) /* Intel Architectural PerfMon
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XEN_CPUFEATURE(TSC_RELIABLE, X86_SYNTH( 4)) /* TSC is known to be reliable */
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XEN_CPUFEATURE(XTOPOLOGY, X86_SYNTH( 5)) /* cpu topology enum extensions */
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XEN_CPUFEATURE(CPUID_FAULTING, X86_SYNTH( 6)) /* cpuid faulting */
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/* Bit 7 unused */
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XEN_CPUFEATURE(XEN_FRED, X86_SYNTH( 7)) /* Xen uses FRED */
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XEN_CPUFEATURE(APERFMPERF, X86_SYNTH( 8)) /* APERFMPERF */
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XEN_CPUFEATURE(MFENCE_RDTSC, X86_SYNTH( 9)) /* MFENCE synchronizes RDTSC */
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XEN_CPUFEATURE(XEN_SMEP, X86_SYNTH(10)) /* SMEP gets used by Xen itself */
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@@ -115,6 +115,17 @@
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#define MCU_OPT_CTRL_GDS_MIT_DIS (_AC(1, ULL) << 4)
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#define MCU_OPT_CTRL_GDS_MIT_LOCK (_AC(1, ULL) << 5)
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#define MSR_FRED_RSP_SL0 0x000001cc
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#define MSR_FRED_RSP_SL1 0x000001cd
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#define MSR_FRED_RSP_SL2 0x000001ce
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#define MSR_FRED_RSP_SL3 0x000001cf
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#define MSR_FRED_STK_LVLS 0x000001d0
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#define MSR_FRED_SSP_SL0 MSR_PL0_SSP
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#define MSR_FRED_SSP_SL1 0x000001d1
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#define MSR_FRED_SSP_SL2 0x000001d2
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#define MSR_FRED_SSP_SL3 0x000001d3
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#define MSR_FRED_CONFIG 0x000001d4
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#define MSR_RTIT_OUTPUT_BASE 0x00000560
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#define MSR_RTIT_OUTPUT_MASK 0x00000561
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#define MSR_RTIT_CTL 0x00000570
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@@ -75,6 +75,7 @@
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#define X86_CR4_PKE 0x00400000 /* enable PKE */
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#define X86_CR4_CET 0x00800000 /* Control-flow Enforcement Technology */
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#define X86_CR4_PKS 0x01000000 /* Protection Key Supervisor */
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#define X86_CR4_FRED (_AC(1, ULL) << 32) /* Fast Return and Event Delivery */
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#define X86_CR8_VALID_MASK 0xf
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@@ -310,7 +310,10 @@ XEN_CPUFEATURE(ARCH_PERF_MON, 10*32+8) /* Architectural Perfmon */
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XEN_CPUFEATURE(FZRM, 10*32+10) /*A Fast Zero-length REP MOVSB */
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XEN_CPUFEATURE(FSRS, 10*32+11) /*A Fast Short REP STOSB */
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XEN_CPUFEATURE(FSRCS, 10*32+12) /*A Fast Short REP CMPSB/SCASB */
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XEN_CPUFEATURE(FRED, 10*32+17) /* Fast Return and Event Delivery */
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XEN_CPUFEATURE(LKGS, 10*32+18) /* Load Kernel GS instruction */
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XEN_CPUFEATURE(WRMSRNS, 10*32+19) /*S WRMSR Non-Serialising */
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XEN_CPUFEATURE(NMI_SRC, 10*32+20) /* NMI-Source Reporting */
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XEN_CPUFEATURE(AMX_FP16, 10*32+21) /* AMX FP16 instruction */
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XEN_CPUFEATURE(AVX_IFMA, 10*32+23) /*A AVX-IFMA Instructions */
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XEN_CPUFEATURE(LAM, 10*32+26) /* Linear Address Masking */
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