mirror of
https://github.com/xen-project/xen.git
synced 2026-10-29 18:50:05 +01:00
xen/arm: use cpumask_t to describe cpu mask in gic_route_dt_irq
Replace by cpumask_t to take advantage of cpumask_* helpers. Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
This commit is contained in:
1 parent
f70263755a
commit
d4e681a59b
3 files changed
+17
-12
No files matched your search
+12
-8
@@ -184,10 +184,14 @@ static hw_irq_controller gic_guest_irq_type = {
|
||||
|
||||
/* needs to be called with gic.lock held */
|
||||
static void gic_set_irq_properties(unsigned int irq, bool_t level,
|
||||
unsigned int cpu_mask, unsigned int priority)
|
||||
const cpumask_t *cpu_mask,
|
||||
unsigned int priority)
|
||||
{
|
||||
volatile unsigned char *bytereg;
|
||||
uint32_t cfg, edgebit;
|
||||
unsigned int mask = cpumask_bits(cpu_mask)[0];
|
||||
|
||||
ASSERT(!(mask & ~0xff)); /* Target bitmap only support 8 CPUS */
|
||||
|
||||
/* Set edge / level */
|
||||
cfg = GICD[GICD_ICFGR + irq / 16];
|
||||
@@ -200,7 +204,7 @@ static void gic_set_irq_properties(unsigned int irq, bool_t level,
|
||||
|
||||
/* Set target CPU mask (RAZ/WI on uniprocessor) */
|
||||
bytereg = (unsigned char *) (GICD + GICD_ITARGETSR);
|
||||
bytereg[irq] = cpu_mask;
|
||||
bytereg[irq] = mask;
|
||||
|
||||
/* Set priority */
|
||||
bytereg = (unsigned char *) (GICD + GICD_IPRIORITYR);
|
||||
@@ -210,12 +214,11 @@ static void gic_set_irq_properties(unsigned int irq, bool_t level,
|
||||
|
||||
/* Program the GIC to route an interrupt */
|
||||
static int gic_route_irq(unsigned int irq, bool_t level,
|
||||
unsigned int cpu_mask, unsigned int priority)
|
||||
const cpumask_t *cpu_mask, unsigned int priority)
|
||||
{
|
||||
struct irq_desc *desc = irq_to_desc(irq);
|
||||
unsigned long flags;
|
||||
|
||||
ASSERT(!(cpu_mask & ~0xff)); /* Targets bitmap only supports 8 CPUs */
|
||||
ASSERT(priority <= 0xff); /* Only 8 bits of priority */
|
||||
ASSERT(irq < gic.lines); /* Can't route interrupts that don't exist */
|
||||
|
||||
@@ -242,7 +245,7 @@ static int gic_route_irq(unsigned int irq, bool_t level,
|
||||
}
|
||||
|
||||
/* Program the GIC to route an interrupt with a dt_irq */
|
||||
void gic_route_dt_irq(const struct dt_irq *irq, unsigned int cpu_mask,
|
||||
void gic_route_dt_irq(const struct dt_irq *irq, const cpumask_t *cpu_mask,
|
||||
unsigned int priority)
|
||||
{
|
||||
bool_t level;
|
||||
@@ -496,7 +499,7 @@ void gic_disable_cpu(void)
|
||||
void gic_route_ppis(void)
|
||||
{
|
||||
/* GIC maintenance */
|
||||
gic_route_dt_irq(&gic.maintenance, 1u << smp_processor_id(), 0xa0);
|
||||
gic_route_dt_irq(&gic.maintenance, cpumask_of(smp_processor_id()), 0xa0);
|
||||
/* Route timer interrupt */
|
||||
route_timer_interrupt();
|
||||
}
|
||||
@@ -511,7 +514,7 @@ void gic_route_spis(void)
|
||||
if ( (irq = serial_dt_irq(seridx)) == NULL )
|
||||
continue;
|
||||
|
||||
gic_route_dt_irq(irq, 1u << smp_processor_id(), 0xa0);
|
||||
gic_route_dt_irq(irq, cpumask_of(smp_processor_id()), 0xa0);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -718,7 +721,8 @@ int gic_route_irq_to_guest(struct domain *d, const struct dt_irq *irq,
|
||||
|
||||
level = dt_irq_is_level_triggered(irq);
|
||||
|
||||
gic_set_irq_properties(irq->irq, level, 1u << smp_processor_id(), 0xa0);
|
||||
gic_set_irq_properties(irq->irq, level, cpumask_of(smp_processor_id()),
|
||||
0xa0);
|
||||
|
||||
retval = __setup_irq(desc, irq->irq, action);
|
||||
if (retval) {
|
||||
|
||||
+3
-3
@@ -222,11 +222,11 @@ static void vtimer_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs)
|
||||
void __cpuinit route_timer_interrupt(void)
|
||||
{
|
||||
gic_route_dt_irq(&timer_irq[TIMER_PHYS_NONSECURE_PPI],
|
||||
1u << smp_processor_id(), 0xa0);
|
||||
cpumask_of(smp_processor_id()), 0xa0);
|
||||
gic_route_dt_irq(&timer_irq[TIMER_HYP_PPI],
|
||||
1u << smp_processor_id(), 0xa0);
|
||||
cpumask_of(smp_processor_id()), 0xa0);
|
||||
gic_route_dt_irq(&timer_irq[TIMER_VIRT_PPI],
|
||||
1u << smp_processor_id(), 0xa0);
|
||||
cpumask_of(smp_processor_id()), 0xa0);
|
||||
}
|
||||
|
||||
/* Set up the timer interrupt on this CPU */
|
||||
|
||||
@@ -148,7 +148,8 @@ extern void vgic_clear_pending_irqs(struct vcpu *v);
|
||||
extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq);
|
||||
|
||||
/* Program the GIC to route an interrupt with a dt_irq */
|
||||
extern void gic_route_dt_irq(const struct dt_irq *irq, unsigned int cpu_mask,
|
||||
extern void gic_route_dt_irq(const struct dt_irq *irq,
|
||||
const cpumask_t *cpu_mask,
|
||||
unsigned int priority);
|
||||
extern void gic_route_ppis(void);
|
||||
extern void gic_route_spis(void);
|
||||
|
||||