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x86/Intel: don't log bogus frequency range on Core/Core2 processors
Models 0F and 17 don't have PLATFORM_INFO documented. While it exists on
at least model 0F, the information there doesn't match the scheme used
on newer models (I'm observing a range of 700 ... 600 MHz reported on a
Xeon E5345).
Sadly the Enhanced Intel Core instance of the table entry is not self-
consistent: The numeric description of the low 3 bits doesn't match the
subsequent more textual description in some of the cases; I'm using the
former here.
Include the older Core model 0E as well as the two other Core2 models,
none of which have respective MSR tables in the SDM.
Fixes: f6b6517cd5 ("x86: retrieve and log CPU frequency information")
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Roger Pau Monné <roger.pau@citrix.com>
This commit is contained in:
1 parent
185250ec78
commit
da4c512b05
1 file changed
+20
@@ -467,6 +467,26 @@ static void intel_log_freq(const struct cpuinfo_x86 *c)
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if ( c->x86 == 6 )
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switch ( c->x86_model )
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{
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static const unsigned short core_factors[] =
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{ 26667, 13333, 20000, 16667, 33333, 10000, 40000 };
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case 0x0e: /* Core */
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case 0x0f: case 0x16: case 0x17: case 0x1d: /* Core2 */
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/*
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* PLATFORM_INFO, while not documented for these, appears to
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* exist in at least some cases, but what it holds doesn't
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* match the scheme used by newer CPUs. At a guess, the min
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* and max fields look to be reversed, while the scaling
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* factor is encoded in FSB_FREQ.
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*/
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if ( min_ratio > max_ratio )
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SWAP(min_ratio, max_ratio);
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if ( rdmsr_safe(MSR_FSB_FREQ, msrval) ||
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(msrval &= 7) >= ARRAY_SIZE(core_factors) )
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return;
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factor = core_factors[msrval];
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break;
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case 0x1a: case 0x1e: case 0x1f: case 0x2e: /* Nehalem */
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case 0x25: case 0x2c: case 0x2f: /* Westmere */
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factor = 13333;
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