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bitkeeper revision 1.59 (3e4fde99RPNgqKfeXcO9RFD8kcDohQ)
Further PCI upgrade to 2.4.21-pre4. moonraider boots with UDMA-100 enabled for IDE discs.
This commit is contained in:
kaf24@labyrinth.cl.cam.ac.uk committed
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5 files changed
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@@ -164,6 +164,8 @@ pci_find_class(unsigned int class, const struct pci_dev *from)
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* %PCI_CAP_ID_MSI Message Signalled Interrupts
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*
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* %PCI_CAP_ID_CHSWP CompactPCI HotSwap
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*
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* %PCI_CAP_ID_PCIX PCI-X
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*/
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int
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pci_find_capability(struct pci_dev *dev, int cap)
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@@ -931,14 +933,13 @@ pdev_set_mwi(struct pci_dev *dev)
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pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cache_size);
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cache_size <<= 2;
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if (cache_size != SMP_CACHE_BYTES) {
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printk(KERN_WARNING "PCI: %s PCI cache line size set incorrectly "
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"(%i bytes) by BIOS/FW, ",
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printk(KERN_WARNING "PCI: %s PCI cache line size set incorrectly (%i bytes) by BIOS/FW.\n",
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dev->slot_name, cache_size);
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if (cache_size > SMP_CACHE_BYTES) {
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printk("expecting %i\n", SMP_CACHE_BYTES);
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printk("PCI: %s cache line size too large - expecting %i.\n", dev->slot_name, SMP_CACHE_BYTES);
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rc = -EINVAL;
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} else {
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printk("correcting to %i\n", SMP_CACHE_BYTES);
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printk("PCI: %s PCI cache line size corrected to %i.\n", dev->slot_name, SMP_CACHE_BYTES);
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
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SMP_CACHE_BYTES >> 2);
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}
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@@ -1038,13 +1039,20 @@ static inline unsigned int pci_calc_resource_flags(unsigned int flags)
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}
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/*
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* Find the extent of a PCI decode..
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* Find the extent of a PCI decode, do sanity checks.
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*/
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static u32 pci_size(u32 base, unsigned long mask)
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static u32 pci_size(u32 base, u32 maxbase, unsigned long mask)
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{
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u32 size = mask & base; /* Find the significant bits */
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u32 size = mask & maxbase; /* Find the significant bits */
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if (!size)
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return 0;
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size = size & ~(size-1); /* Get the lowest of them to find the decode size */
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return size-1; /* extent = size - 1 */
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size -= 1; /* extent = size - 1 */
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if (base == maxbase && ((base | size) & mask) != mask)
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return 0; /* base == maxbase can be valid only
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if the BAR has been already
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programmed with all 1s */
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return size;
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}
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static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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@@ -1067,13 +1075,17 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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if (l == 0xffffffff)
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l = 0;
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if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
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sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK);
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if (!sz)
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continue;
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res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
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res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
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sz = pci_size(sz, PCI_BASE_ADDRESS_MEM_MASK);
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} else {
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sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
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if (!sz)
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continue;
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res->start = l & PCI_BASE_ADDRESS_IO_MASK;
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res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
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sz = pci_size(sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
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}
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res->end = res->start + (unsigned long) sz;
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res->flags |= pci_calc_resource_flags(l);
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@@ -1103,6 +1115,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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if (rom) {
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dev->rom_base_reg = rom;
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res = &dev->resource[PCI_ROM_RESOURCE];
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res->name = dev->name;
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pci_read_config_dword(dev, rom, &l);
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pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
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pci_read_config_dword(dev, rom, &sz);
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@@ -1110,13 +1123,14 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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if (l == 0xffffffff)
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l = 0;
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if (sz && sz != 0xffffffff) {
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sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK);
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if (!sz)
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return;
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res->flags = (l & PCI_ROM_ADDRESS_ENABLE) |
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IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
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res->start = l & PCI_ROM_ADDRESS_MASK;
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sz = pci_size(sz, PCI_ROM_ADDRESS_MASK);
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res->end = res->start + (unsigned long) sz;
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}
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res->name = dev->name;
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}
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}
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@@ -1731,6 +1745,7 @@ pci_pm_callback(struct pm_dev *pm_device, pm_request_t rqst, void *data)
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#endif
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#if 0 /* XXX KAF: Only USB uses this stuff -- I think we'll just bin it. */
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/*
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@@ -2158,6 +2173,8 @@ EXPORT_SYMBOL(pci_add_new_bus);
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EXPORT_SYMBOL(pci_do_scan_bus);
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EXPORT_SYMBOL(pci_scan_slot);
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EXPORT_SYMBOL(pci_scan_bus);
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EXPORT_SYMBOL(pci_scan_device);
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EXPORT_SYMBOL(pci_read_bridge_bases);
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#ifdef CONFIG_PROC_FS
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EXPORT_SYMBOL(pci_proc_attach_device);
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EXPORT_SYMBOL(pci_proc_detach_device);
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@@ -582,6 +582,7 @@
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6003 CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator]
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1013 4280 Crystal SoundFusion PCI Audio Accelerator
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1681 0050 Hercules Game Theater XP
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1681 a011 Hercules Fortissimo III 7.1
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6004 CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator]
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6005 Crystal CS4281 PCI Audio
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1013 4281 Crystal CS4281 PCI Audio
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@@ -2617,6 +2618,7 @@
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10fc I-O Data Device, Inc.
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# What's in the cardbus end of a Sony ACR-A01 card, comes with newer Vaio CD-RW drives
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0003 Cardbus IDE Controller
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0005 Cardbus SCSI CBSC II
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10fd Soyo Computer, Inc
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10fe Fast Multimedia AG
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10ff NCube
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@@ -2678,6 +2680,7 @@
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0505 VT82C505
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0561 VT82C561
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0571 VT82C586B PIPC Bus Master IDE
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1458 5002 GA-7VAX Mainboard
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0576 VT82C576 3V [Apollo Master]
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0585 VT82C585VP [Apollo VP1/VPX]
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0586 VT82C586/A/B PCI-to-ISA [Apollo VP]
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@@ -2726,6 +2729,7 @@
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1462 3091 MS-6309 Onboard Audio
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15dd 7609 Onboard Audio
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3059 VT8233 AC97 Audio Controller
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1458 a002 GA-7VAX Onboard Audio (Realtek ALC650)
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3065 VT6102 [Rhine-II]
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1186 1400 DFE-530TX rev A
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1186 1401 DFE-530TX rev B
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@@ -2739,6 +2743,7 @@
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3102 VT8662 Host Bridge
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3103 VT8615 Host Bridge
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3104 USB 2.0
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1458 5004 GA-7VAX Mainboard
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3109 VT8233C PCI to ISA Bridge
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3112 VT8361 [KLE133] Host Bridge
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3128 VT8753 [P4X266 AGP]
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@@ -2747,6 +2752,9 @@
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3148 P4M266 Host Bridge
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3156 P/KN266 Host Bridge
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3177 VT8233A ISA Bridge
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1458 5001 GA-7VAX Mainboard
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3189 VT8377 [KT400 AGP] Host Bridge
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1458 5000 GA-7VAX Mainboard
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5030 VT82C596 ACPI [Apollo PRO]
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6100 VT85C100A [Rhine II]
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8231 VT8231 [PCI-to-ISA Bridge]
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@@ -2767,6 +2775,7 @@
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b102 VT8362 AGP Bridge
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b103 VT8615 AGP Bridge
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b112 VT8361 [KLE133] AGP Bridge
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b168 VT8235 PCI Bridge
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1107 Stratus Computers
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0576 VIA VT82C570MV [Apollo] (Wrong vendor ID!)
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1108 Proteon, Inc.
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@@ -3027,6 +3036,12 @@
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1144 Cincinnati Milacron
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0001 Noservo controller
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1145 Workbit Corporation
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f007 NinjaSCSI-32 KME
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8007 NinjaSCSI-32 Workbit
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f010 NinjaSCSI-32 Workbit
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f012 NinjaSCSI-32 Logitec
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f013 NinjaSCSI-32 Logitec
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f015 NinjaSCSI-32 Melco
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1146 Force Computers
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1147 Interface Corp
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1148 Syskonnect (Schneider & Koch)
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@@ -167,6 +167,21 @@ static void __init quirk_vsfx(struct pci_dev *dev)
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}
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}
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/*
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* Ali Magik requires workarounds to be used by the drivers
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* that DMA to AGP space. Latency must be set to 0xA and triton
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* workaround applied too
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* [Info kindly provided by ALi]
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*/
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static void __init quirk_alimagik(struct pci_dev *dev)
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{
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if((pci_pci_problems&PCIPCI_ALIMAGIK)==0)
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{
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printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
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pci_pci_problems|=PCIPCI_ALIMAGIK|PCIPCI_TRITON;
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}
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}
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/*
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* Natoma has some interesting boundary conditions with Zoran stuff
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@@ -211,6 +226,19 @@ static void __init quirk_io_region(struct pci_dev *dev, unsigned region, unsigne
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}
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}
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/*
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* ATI Northbridge setups MCE the processor if you even
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* read somewhere between 0x3b0->0x3bb or read 0x3d3
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*/
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static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
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{
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printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
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/* Mae rhaid in i beidio a edrych ar y lleoliad I/O hyn */
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request_region(0x3b0, 0x0C, "RadeonIGP");
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request_region(0x3d3, 0x01, "RadeonIGP");
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}
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/*
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* Let's make the southbridge information explicit instead
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* of having to worry about people probing the ACPI areas,
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@@ -494,6 +522,56 @@ static void __init quirk_mediagx_master(struct pci_dev *dev)
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}
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}
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/*
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* As per PCI spec, ignore base address registers 0-3 of the IDE controllers
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* running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
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* secondary channels respectively). If the device reports Compatible mode
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* but does use BAR0-3 for address decoding, we assume that firmware has
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* programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
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* Exceptions (if they exist) must be handled in chip/architecture specific
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* fixups.
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*
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* Note: for non x86 people. You may need an arch specific quirk to handle
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* moving IDE devices to native mode as well. Some plug in card devices power
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* up in compatible mode and assume the BIOS will adjust them.
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*
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* Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
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* we do now ? We don't want is pci_enable_device to come along
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* and assign new resources. Both approaches work for that.
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*/
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static void __devinit quirk_ide_bases(struct pci_dev *dev)
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{
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struct resource *res;
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int first_bar = 2, last_bar = 0;
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if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
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return;
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res = &dev->resource[0];
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/* primary channel: ProgIf bit 0, BAR0, BAR1 */
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if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
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res[0].start = res[0].end = res[0].flags = 0;
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res[1].start = res[1].end = res[1].flags = 0;
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first_bar = 0;
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last_bar = 1;
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}
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/* secondary channel: ProgIf bit 2, BAR2, BAR3 */
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if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
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res[2].start = res[2].end = res[2].flags = 0;
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res[3].start = res[3].end = res[3].flags = 0;
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last_bar = 3;
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}
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if (!last_bar)
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return;
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printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
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first_bar, last_bar, dev->slot_name);
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}
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/*
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* The main table of quirks.
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*/
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@@ -521,6 +599,8 @@ static struct pci_fixup pci_fixups[] __initdata = {
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{ PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma },
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{ PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma },
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{ PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma },
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{ PCI_FIXUP_FINAL, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik },
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{ PCI_FIXUP_FINAL, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik },
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{ PCI_FIXUP_FINAL, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci },
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{ PCI_FIXUP_FINAL, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci },
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{ PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency },
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@@ -535,6 +615,7 @@ static struct pci_fixup pci_fixups[] __initdata = {
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{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi },
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{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb },
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{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb },
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{ PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases },
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{ PCI_FIXUP_FINAL, PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy },
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#ifdef CONFIG_X86_IO_APIC
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@@ -548,6 +629,7 @@ static struct pci_fixup pci_fixups[] __initdata = {
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{ PCI_FIXUP_FINAL, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic },
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{ PCI_FIXUP_FINAL, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering },
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{ PCI_FIXUP_FINAL, PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_IGP, quirk_ati_exploding_mce },
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/*
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* i82380FB mobile docking controller: its PCI-to-PCI bridge
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* is subtractive decoding (transparent), and does indicate this
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@@ -65,9 +65,9 @@
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#define PCI_HEADER_TYPE_CARDBUS 2
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#define PCI_BIST 0x0f /* 8 bits */
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#define PCI_BIST_CODE_MASK 0x0f /* Return result */
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#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
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#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
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#define PCI_BIST_CODE_MASK 0x0f /* Return result */
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#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
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#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
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/*
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* Base addresses specify locations in memory or I/O space.
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@@ -195,6 +195,7 @@
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#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
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#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
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#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
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#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
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#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
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#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
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#define PCI_CAP_SIZEOF 4
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@@ -271,6 +272,37 @@
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#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
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#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
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/* CompactPCI Hotswap Register */
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||||
#define PCI_CHSWP_CSR 2 /* Control and Status Register */
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#define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
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#define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
|
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#define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
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#define PCI_CHSWP_LOO 0x08 /* LED On / Off */
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#define PCI_CHSWP_PI 0x30 /* Programming Interface */
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#define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
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#define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
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|
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/* PCI-X registers */
|
||||
|
||||
#define PCI_X_CMD 2 /* Modes & Features */
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||||
#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
|
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#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
|
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#define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
|
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#define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
|
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#define PCI_X_DEVFN 4 /* A copy of devfn. */
|
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#define PCI_X_BUSNR 5 /* Bus segment number */
|
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#define PCI_X_STATUS 6 /* PCI-X capabilities */
|
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#define PCI_X_STATUS_64BIT 0x0001 /* 64-bit device */
|
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#define PCI_X_STATUS_133MHZ 0x0002 /* 133 MHz capable */
|
||||
#define PCI_X_STATUS_SPL_DISC 0x0004 /* Split Completion Discarded */
|
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#define PCI_X_STATUS_UNX_SPL 0x0008 /* Unexpected Split Completion */
|
||||
#define PCI_X_STATUS_COMPLEX 0x0010 /* Device Complexity */
|
||||
#define PCI_X_STATUS_MAX_READ 0x0060 /* Designed Maximum Memory Read Count */
|
||||
#define PCI_X_STATUS_MAX_SPLIT 0x0380 /* Design Max Outstanding Split Trans */
|
||||
#define PCI_X_STATUS_MAX_CUM 0x1c00 /* Designed Max Cumulative Read Size */
|
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#define PCI_X_STATUS_SPL_ERR 0x2000 /* Rcvd Split Completion Error Msg */
|
||||
|
||||
/* Include the ID list */
|
||||
|
||||
#include <linux/pci_ids.h>
|
||||
@@ -769,6 +801,7 @@ extern int pci_pci_problems;
|
||||
#define PCIPCI_NATOMA 4
|
||||
#define PCIPCI_VIAETBF 8
|
||||
#define PCIPCI_VSFX 16
|
||||
#define PCIPCI_ALIMAGIK 32
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* LINUX_PCI_H */
|
||||
@@ -136,6 +136,7 @@
|
||||
#define PCI_DEVICE_ID_COMPAQ_TACHYON 0xa0fc
|
||||
#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10
|
||||
#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32
|
||||
#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33
|
||||
#define PCI_DEVICE_ID_COMPAQ_NETEL10 0xae34
|
||||
#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35
|
||||
#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40
|
||||
@@ -143,6 +144,7 @@
|
||||
#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011
|
||||
#define PCI_DEVICE_ID_COMPAQ_CISS 0xb060
|
||||
#define PCI_DEVICE_ID_COMPAQ_CISSB 0xb178
|
||||
#define PCI_DEVICE_ID_COMPAQ_CISSC 0x0046
|
||||
#define PCI_DEVICE_ID_COMPAQ_THUNDER 0xf130
|
||||
#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150
|
||||
|
||||
@@ -172,6 +174,8 @@
|
||||
#define PCI_DEVICE_ID_LSI_FC929_LAN 0x0623
|
||||
#define PCI_DEVICE_ID_LSI_FC919 0x0624
|
||||
#define PCI_DEVICE_ID_LSI_FC919_LAN 0x0625
|
||||
#define PCI_DEVICE_ID_LSI_FC929X 0x0626
|
||||
#define PCI_DEVICE_ID_LSI_FC919X 0x0628
|
||||
#define PCI_DEVICE_ID_NCR_YELLOWFIN 0x0701
|
||||
#define PCI_DEVICE_ID_LSI_61C102 0x0901
|
||||
#define PCI_DEVICE_ID_LSI_63C815 0x1000
|
||||
@@ -265,6 +269,8 @@
|
||||
#define PCI_DEVICE_ID_ATI_RADEON_RB 0x5145
|
||||
#define PCI_DEVICE_ID_ATI_RADEON_RC 0x5146
|
||||
#define PCI_DEVICE_ID_ATI_RADEON_RD 0x5147
|
||||
/* RadeonIGP */
|
||||
#define PCI_DEVICE_ID_ATI_RADEON_IGP 0xCAB0
|
||||
|
||||
#define PCI_VENDOR_ID_VLSI 0x1004
|
||||
#define PCI_DEVICE_ID_VLSI_82C592 0x0005
|
||||
@@ -288,6 +294,12 @@
|
||||
#define PCI_DEVICE_ID_NS_87560_USB 0x0012
|
||||
#define PCI_DEVICE_ID_NS_83815 0x0020
|
||||
#define PCI_DEVICE_ID_NS_83820 0x0022
|
||||
#define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500
|
||||
#define PCI_DEVICE_ID_NS_SCx200_SMI 0x0501
|
||||
#define PCI_DEVICE_ID_NS_SCx200_IDE 0x0502
|
||||
#define PCI_DEVICE_ID_NS_SCx200_AUDIO 0x0503
|
||||
#define PCI_DEVICE_ID_NS_SCx200_VIDEO 0x0504
|
||||
#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505
|
||||
#define PCI_DEVICE_ID_NS_87410 0xd001
|
||||
|
||||
#define PCI_VENDOR_ID_TSENG 0x100c
|
||||
@@ -372,7 +384,7 @@
|
||||
#define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006
|
||||
#define PCI_DEVICE_ID_AMD_FE_GATE_7007 0x7007
|
||||
#define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C
|
||||
#define PCI_DEVIDE_ID_AMD_FE_GATE_700D 0x700D
|
||||
#define PCI_DEVICE_ID_AMD_FE_GATE_700D 0x700D
|
||||
#define PCI_DEVICE_ID_AMD_FE_GATE_700E 0x700E
|
||||
#define PCI_DEVICE_ID_AMD_FE_GATE_700F 0x700F
|
||||
#define PCI_DEVICE_ID_AMD_COBRA_7400 0x7400
|
||||
@@ -387,11 +399,19 @@
|
||||
#define PCI_DEVICE_ID_AMD_VIPER_7411 0x7411
|
||||
#define PCI_DEVICE_ID_AMD_VIPER_7413 0x7413
|
||||
#define PCI_DEVICE_ID_AMD_VIPER_7414 0x7414
|
||||
#define PCI_DEVICE_ID_AMD_VIPER_7440 0x7440
|
||||
#define PCI_DEVICE_ID_AMD_VIPER_7441 0x7441
|
||||
#define PCI_DEVICE_ID_AMD_VIPER_7443 0x7443
|
||||
#define PCI_DEVICE_ID_AMD_VIPER_7448 0x7448
|
||||
#define PCI_DEVICE_ID_AMD_VIPER_7449 0x7449
|
||||
#define PCI_DEVICE_ID_AMD_OPUS_7440 0x7440
|
||||
# define PCI_DEVICE_ID_AMD_VIPER_7440 PCI_DEVICE_ID_AMD_OPUS_7440
|
||||
#define PCI_DEVICE_ID_AMD_OPUS_7441 0x7441
|
||||
# define PCI_DEVICE_ID_AMD_VIPER_7441 PCI_DEVICE_ID_AMD_OPUS_7441
|
||||
#define PCI_DEVICE_ID_AMD_OPUS_7443 0x7443
|
||||
# define PCI_DEVICE_ID_AMD_VIPER_7443 PCI_DEVICE_ID_AMD_OPUS_7443
|
||||
#define PCI_DEVICE_ID_AMD_OPUS_7448 0x7448
|
||||
# define PCI_DEVICE_ID_AMD_VIPER_7448 PCI_DEVICE_ID_AMD_OPUS_7448
|
||||
#define PCI_DEVICE_ID_AMD_OPUS_7449 0x7449
|
||||
# define PCI_DEVICE_ID_AMD_VIPER_7449 PCI_DEVICE_ID_AMD_OPUS_7449
|
||||
#define PCI_DEVICE_ID_AMD_8111_LAN 0x7462
|
||||
#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469
|
||||
#define PCI_DEVICE_ID_AMD_8111_AC97 0x746d
|
||||
|
||||
#define PCI_VENDOR_ID_TRIDENT 0x1023
|
||||
#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
|
||||
@@ -518,6 +538,8 @@
|
||||
#define PCI_DEVICE_ID_HP_DIVA1 0x1049
|
||||
#define PCI_DEVICE_ID_HP_DIVA2 0x104A
|
||||
#define PCI_DEVICE_ID_HP_SP2_0 0x104B
|
||||
#define PCI_DEVICE_ID_HP_REO_SBA 0x10f0
|
||||
#define PCI_DEVICE_ID_HP_REO_IOC 0x10f1
|
||||
#define PCI_DEVICE_ID_HP_ZX1_SBA 0x1229
|
||||
#define PCI_DEVICE_ID_HP_ZX1_IOC 0x122a
|
||||
#define PCI_DEVICE_ID_HP_ZX1_LBA 0x122e
|
||||
@@ -605,6 +627,7 @@
|
||||
#define PCI_VENDOR_ID_MOTOROLA_OOPS 0x1507
|
||||
#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001
|
||||
#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002
|
||||
#define PCI_DEVICE_ID_MOTOROLA_MPC107 0x0004
|
||||
#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801
|
||||
#define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802
|
||||
#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803
|
||||
@@ -617,8 +640,7 @@
|
||||
#define PCI_DEVICE_ID_PROMISE_20262 0x4d38
|
||||
#define PCI_DEVICE_ID_PROMISE_20263 0x0D38
|
||||
#define PCI_DEVICE_ID_PROMISE_20268 0x4d68
|
||||
#define PCI_DEVICE_ID_PROMISE_20268R 0x6268
|
||||
#define PCI_DEVICE_ID_PROMISE_20270 0x6268 /* XXX IAP */
|
||||
#define PCI_DEVICE_ID_PROMISE_20270 0x6268
|
||||
#define PCI_DEVICE_ID_PROMISE_20269 0x4d69
|
||||
#define PCI_DEVICE_ID_PROMISE_20271 0x6269
|
||||
#define PCI_DEVICE_ID_PROMISE_20275 0x1275
|
||||
@@ -746,6 +768,9 @@
|
||||
#define PCI_DEVICE_ID_CMD_670 0x0670
|
||||
#define PCI_DEVICE_ID_CMD_680 0x0680
|
||||
|
||||
#define PCI_DEVICE_ID_SII_680 0x0680
|
||||
#define PCI_DEVICE_ID_SII_3112 0x3112
|
||||
|
||||
#define PCI_VENDOR_ID_VISION 0x1098
|
||||
#define PCI_DEVICE_ID_VISION_QD8500 0x0001
|
||||
#define PCI_DEVICE_ID_VISION_QD8580 0x0002
|
||||
@@ -821,6 +846,7 @@
|
||||
#define PCI_DEVICE_ID_AL_M1523 0x1523
|
||||
#define PCI_DEVICE_ID_AL_M1531 0x1531
|
||||
#define PCI_DEVICE_ID_AL_M1533 0x1533
|
||||
#define PCI_DEVICE_ID_AL_M1535 0x1535
|
||||
#define PCI_DEVICE_ID_AL_M1541 0x1541
|
||||
#define PCI_DEVICE_ID_AL_M1621 0x1621
|
||||
#define PCI_DEVICE_ID_AL_M1631 0x1631
|
||||
@@ -875,6 +901,7 @@
|
||||
#define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029
|
||||
#define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C
|
||||
#define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D
|
||||
#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE 0x0065
|
||||
#define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0
|
||||
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100
|
||||
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101
|
||||
@@ -888,6 +915,7 @@
|
||||
#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152
|
||||
#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153
|
||||
#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0
|
||||
#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE 0x01bc
|
||||
#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200
|
||||
#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1 0x0201
|
||||
#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2 0x0202
|
||||
@@ -922,6 +950,7 @@
|
||||
#define PCI_DEVICE_ID_REALTEK_8029 0x8029
|
||||
#define PCI_DEVICE_ID_REALTEK_8129 0x8129
|
||||
#define PCI_DEVICE_ID_REALTEK_8139 0x8139
|
||||
#define PCI_DEVICE_ID_REALTEK_8169 0x8169
|
||||
|
||||
#define PCI_VENDOR_ID_XILINX 0x10ee
|
||||
#define PCI_DEVICE_ID_TURBOPAM 0x4020
|
||||
@@ -988,7 +1017,10 @@
|
||||
#define PCI_DEVICE_ID_VIA_8233C_0 0x3109
|
||||
#define PCI_DEVICE_ID_VIA_8361 0x3112
|
||||
#define PCI_DEVICE_ID_VIA_8233A 0x3147
|
||||
#define PCI_DEVICE_ID_VIA_8235 0x3177
|
||||
#define PCI_DEVICE_ID_VIA_P4X333 0x3168
|
||||
#define PCI_DEVICE_ID_VIA_8235 0x3177
|
||||
#define PCI_DEVICE_ID_VIA_8377_0 0x3189
|
||||
#define PCI_DEVICE_ID_VIA_8377_0 0x3189
|
||||
#define PCI_DEVICE_ID_VIA_86C100A 0x6100
|
||||
#define PCI_DEVICE_ID_VIA_8231 0x8231
|
||||
#define PCI_DEVICE_ID_VIA_8231_4 0x8235
|
||||
@@ -1067,6 +1099,7 @@
|
||||
#define PCI_DEVICE_ID_EICON_DIVA20PRO_U 0xe003
|
||||
#define PCI_DEVICE_ID_EICON_DIVA20_U 0xe004
|
||||
#define PCI_DEVICE_ID_EICON_DIVA201 0xe005
|
||||
#define PCI_DEVICE_ID_EICON_DIVA202 0xe00b
|
||||
#define PCI_DEVICE_ID_EICON_MAESTRA 0xe010
|
||||
#define PCI_DEVICE_ID_EICON_MAESTRAQ 0xe012
|
||||
#define PCI_DEVICE_ID_EICON_MAESTRAQ_U 0xe013
|
||||
@@ -1571,6 +1604,9 @@
|
||||
#define PCI_VENDOR_ID_TEKRAM 0x1de1
|
||||
#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29
|
||||
|
||||
#define PCI_VENDOR_ID_HINT 0x3388
|
||||
#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013
|
||||
|
||||
#define PCI_VENDOR_ID_3DLABS 0x3d3d
|
||||
#define PCI_DEVICE_ID_3DLABS_300SX 0x0001
|
||||
#define PCI_DEVICE_ID_3DLABS_500TX 0x0002
|
||||
@@ -1634,6 +1670,9 @@
|
||||
#define PCI_DEVICE_ID_INTEL_I960 0x0960
|
||||
#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
|
||||
#define PCI_DEVICE_ID_INTEL_82562ET 0x1031
|
||||
|
||||
#define PCI_DEVICE_ID_INTEL_82815_MC 0x1130
|
||||
|
||||
#define PCI_DEVICE_ID_INTEL_82559ER 0x1209
|
||||
#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221
|
||||
#define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222
|
||||
|
||||