x86: Remove jiffies usage.

Jiffies will be obsolete in x86 after PIT timer interupt is disabled,
so this patch replace jiffies usage with NOW() API.

Signed-off-by: Yu Ke <ke.yu@intel.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
This commit is contained in:
Keir Fraser committed 2008-04-10 10:12:04 +01:00
1 parent 5f74ef6277
commit dacde68ff1
9 files changed
+43 -39

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+7 -2
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@@ -1244,7 +1244,11 @@ static void __init setup_ioapic_ids_from_mpc(void) { }
*/
static int __init timer_irq_works(void)
{
unsigned long t1 = jiffies;
extern unsigned long pit0_ticks;
unsigned long t1;
t1 = pit0_ticks;
mb();
local_irq_enable();
/* Let ten ticks pass... */
@@ -1257,7 +1261,8 @@ static int __init timer_irq_works(void)
* might have cached one ExtINT interrupt. Finally, at
* least one tick may be lost due to delays.
*/
if (jiffies - t1 > 4)
mb();
if (pit0_ticks - t1 > 4)
return 1;
return 0;
+2 -3
View File
@@ -40,7 +40,7 @@ string_param("clocksource", opt_clocksource);
unsigned long cpu_khz; /* CPU clock frequency in kHz. */
unsigned long hpet_address;
DEFINE_SPINLOCK(rtc_lock);
volatile unsigned long jiffies;
unsigned long pit0_ticks;
static u32 wc_sec, wc_nsec; /* UTC time at last 'time update'. */
static DEFINE_SPINLOCK(wc_lock);
@@ -150,8 +150,7 @@ void timer_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs)
{
ASSERT(local_irq_is_enabled());
/* Update jiffies counter. */
(*(volatile unsigned long *)&jiffies)++;
(*(volatile unsigned long *)&pit0_ticks)++;
/* Rough hack to allow accurate timers to sort-of-work with no APIC. */
if ( !cpu_has_apic )
+2 -6
View File
@@ -92,14 +92,10 @@ struct acpi_rmrr_unit * acpi_find_matched_rmrr_unit(struct pci_dev *dev);
#define RMRR_TYPE 2
#define ATSR_TYPE 3
#define DMAR_OPERATION_TIMEOUT (HZ*60) /* 1m */
#define time_after(a,b) \
(typecheck(unsigned long, a) && \
typecheck(unsigned long, b) && \
((long)(b) - (long)(a) < 0))
#define DMAR_OPERATION_TIMEOUT MILLISECS(1000)
int vtd_hw_check(void);
void disable_pmr(struct iommu *iommu);
int is_usb_device(struct pci_dev *pdev);
#endif // _DMAR_H_
#endif /* _DMAR_H_ */
+8 -7
View File
@@ -21,6 +21,7 @@
#include <xen/irq.h>
#include <xen/sched.h>
#include <xen/iommu.h>
#include <xen/time.h>
#include "iommu.h"
#include "dmar.h"
#include "vtd.h"
@@ -244,7 +245,7 @@ io_apic_write_remap_rte(
int intremap_setup(struct iommu *iommu)
{
struct ir_ctrl *ir_ctrl;
unsigned long start_time;
s_time_t start_time;
if ( !ecap_intr_remap(iommu->ecap) )
return -ENODEV;
@@ -275,10 +276,10 @@ int intremap_setup(struct iommu *iommu)
dmar_writel(iommu->reg, DMAR_GCMD_REG, iommu->gcmd);
/* Make sure hardware complete it */
start_time = jiffies;
start_time = NOW();
while ( !(dmar_readl(iommu->reg, DMAR_GSTS_REG) & DMA_GSTS_SIRTPS) )
{
if ( time_after(jiffies, start_time + DMAR_OPERATION_TIMEOUT) )
if ( NOW() > (start_time + DMAR_OPERATION_TIMEOUT) )
{
dprintk(XENLOG_ERR VTDPREFIX,
"Cannot set SIRTP field for interrupt remapping\n");
@@ -291,10 +292,10 @@ int intremap_setup(struct iommu *iommu)
iommu->gcmd |= DMA_GCMD_CFI;
dmar_writel(iommu->reg, DMAR_GCMD_REG, iommu->gcmd);
start_time = jiffies;
start_time = NOW();
while ( !(dmar_readl(iommu->reg, DMAR_GSTS_REG) & DMA_GSTS_CFIS) )
{
if ( time_after(jiffies, start_time + DMAR_OPERATION_TIMEOUT) )
if ( NOW() > (start_time + DMAR_OPERATION_TIMEOUT) )
{
dprintk(XENLOG_ERR VTDPREFIX,
"Cannot set CFI field for interrupt remapping\n");
@@ -307,10 +308,10 @@ int intremap_setup(struct iommu *iommu)
iommu->gcmd |= DMA_GCMD_IRE;
dmar_writel(iommu->reg, DMAR_GCMD_REG, iommu->gcmd);
start_time = jiffies;
start_time = NOW();
while ( !(dmar_readl(iommu->reg, DMAR_GSTS_REG) & DMA_GSTS_IRES) )
{
if ( time_after(jiffies, start_time + DMAR_OPERATION_TIMEOUT) )
if ( NOW() > (start_time + DMAR_OPERATION_TIMEOUT) )
{
dprintk(XENLOG_ERR VTDPREFIX,
"Cannot set IRE field for interrupt remapping\n");
+10 -9
View File
@@ -26,6 +26,7 @@
#include <asm/paging.h>
#include <xen/iommu.h>
#include <xen/numa.h>
#include <xen/time.h>
#include "iommu.h"
#include "dmar.h"
#include "../pci-direct.h"
@@ -356,7 +357,7 @@ static void iommu_flush_write_buffer(struct iommu *iommu)
{
u32 val;
unsigned long flag;
unsigned long start_time;
s_time_t start_time;
if ( !cap_rwbf(iommu->cap) )
return;
@@ -366,13 +367,13 @@ static void iommu_flush_write_buffer(struct iommu *iommu)
dmar_writel(iommu->reg, DMAR_GCMD_REG, val);
/* Make sure hardware complete it */
start_time = jiffies;
start_time = NOW();
for ( ; ; )
{
val = dmar_readl(iommu->reg, DMAR_GSTS_REG);
if ( !(val & DMA_GSTS_WBFS) )
break;
if ( time_after(jiffies, start_time + DMAR_OPERATION_TIMEOUT) )
if ( NOW() > start_time + DMAR_OPERATION_TIMEOUT )
panic("DMAR hardware is malfunctional,"
" please disable IOMMU\n");
cpu_relax();
@@ -389,7 +390,7 @@ static int flush_context_reg(
struct iommu *iommu = (struct iommu *) _iommu;
u64 val = 0;
unsigned long flag;
unsigned long start_time;
s_time_t start_time;
/*
* In the non-present entry flush case, if hardware doesn't cache
@@ -427,13 +428,13 @@ static int flush_context_reg(
dmar_writeq(iommu->reg, DMAR_CCMD_REG, val);
/* Make sure hardware complete it */
start_time = jiffies;
start_time = NOW();
for ( ; ; )
{
val = dmar_readq(iommu->reg, DMAR_CCMD_REG);
if ( !(val & DMA_CCMD_ICC) )
break;
if ( time_after(jiffies, start_time + DMAR_OPERATION_TIMEOUT) )
if ( NOW() > start_time + DMAR_OPERATION_TIMEOUT )
panic("DMAR hardware is malfunctional, please disable IOMMU\n");
cpu_relax();
}
@@ -477,7 +478,7 @@ static int flush_iotlb_reg(void *_iommu, u16 did,
int tlb_offset = ecap_iotlb_offset(iommu->ecap);
u64 val = 0, val_iva = 0;
unsigned long flag;
unsigned long start_time;
s_time_t start_time;
/*
* In the non-present entry flush case, if hardware doesn't cache
@@ -524,13 +525,13 @@ static int flush_iotlb_reg(void *_iommu, u16 did,
dmar_writeq(iommu->reg, tlb_offset + 8, val);
/* Make sure hardware complete it */
start_time = jiffies;
start_time = NOW();
for ( ; ; )
{
val = dmar_readq(iommu->reg, tlb_offset + 8);
if ( !(val & DMA_TLB_IVT) )
break;
if ( time_after(jiffies, start_time + DMAR_OPERATION_TIMEOUT) )
if ( NOW() > start_time + DMAR_OPERATION_TIMEOUT )
panic("DMAR hardware is malfunctional, please disable IOMMU\n");
cpu_relax();
}
+8 -7
View File
@@ -21,6 +21,7 @@
#include <xen/sched.h>
#include <xen/iommu.h>
#include <xen/time.h>
#include "iommu.h"
#include "dmar.h"
#include "vtd.h"
@@ -183,7 +184,7 @@ static int queue_invalidate_wait(struct iommu *iommu,
u8 iflag, u8 sw, u8 fn, u32 sdata, volatile u32 *saddr)
{
unsigned long flags;
unsigned long start_time;
s_time_t start_time;
int index = -1;
int ret = -1;
struct qi_ctrl *qi_ctrl = iommu_qi_ctrl(iommu);
@@ -201,10 +202,10 @@ static int queue_invalidate_wait(struct iommu *iommu,
if ( sw )
{
/* In case all wait descriptor writes to same addr with same data */
start_time = jiffies;
start_time = NOW();
while ( *saddr != 1 )
{
if ( time_after(jiffies, start_time + DMAR_OPERATION_TIMEOUT) )
if ( NOW() > (start_time + DMAR_OPERATION_TIMEOUT) )
{
print_qi_regs(iommu);
panic("queue invalidate wait descriptor was not executed\n");
@@ -414,7 +415,7 @@ static int flush_iotlb_qi(
int qinval_setup(struct iommu *iommu)
{
unsigned long start_time;
s_time_t start_time;
u32 status = 0;
struct qi_ctrl *qi_ctrl;
struct iommu_flush *flush;
@@ -448,13 +449,13 @@ int qinval_setup(struct iommu *iommu)
dmar_writel(iommu->reg, DMAR_GCMD_REG, iommu->gcmd);
/* Make sure hardware complete it */
start_time = jiffies;
while ( 1 )
start_time = NOW();
for ( ; ; )
{
status = dmar_readl(iommu->reg, DMAR_GSTS_REG);
if ( status & DMA_GSTS_QIES )
break;
if ( time_after(jiffies, start_time + DMAR_OPERATION_TIMEOUT) )
if ( NOW() > (start_time + DMAR_OPERATION_TIMEOUT) )
panic("Cannot set QIE field for queue invalidation\n");
cpu_relax();
}
+4 -3
View File
@@ -20,6 +20,7 @@
#include <xen/sched.h>
#include <xen/delay.h>
#include <xen/iommu.h>
#include <xen/time.h>
#include "iommu.h"
#include "dmar.h"
#include "../pci-direct.h"
@@ -69,7 +70,7 @@ int vtd_hw_check(void)
/* Disable vt-d protected memory registers. */
void disable_pmr(struct iommu *iommu)
{
unsigned long start_time;
s_time_t start_time;
unsigned int val;
val = dmar_readl(iommu->reg, DMAR_PMEN_REG);
@@ -77,7 +78,7 @@ void disable_pmr(struct iommu *iommu)
return;
dmar_writel(iommu->reg, DMAR_PMEN_REG, val & ~DMA_PMEN_EPM);
start_time = jiffies;
start_time = NOW();
for ( ; ; )
{
@@ -85,7 +86,7 @@ void disable_pmr(struct iommu *iommu)
if ( (val & DMA_PMEN_PRS) == 0 )
break;
if ( time_after(jiffies, start_time + DMAR_OPERATION_TIMEOUT) )
if ( NOW() > start_time + DMAR_OPERATION_TIMEOUT )
panic("Disable PMRs timeout\n");
cpu_relax();
+2
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@@ -18,6 +18,8 @@ struct p2m_entry;
struct tlb_track;
#endif
extern unsigned long volatile jiffies;
struct vcpu;
extern void relinquish_vcpu_resources(struct vcpu *v);
extern int vcpu_late_initialise(struct vcpu *v);
-2
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@@ -25,8 +25,6 @@
DEFINE_XEN_GUEST_HANDLE(vcpu_runstate_info_compat_t);
#endif
extern unsigned long volatile jiffies;
/* A global pointer to the initial domain (DOM0). */
extern struct domain *dom0;
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