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mini-os: arm: boot code
Based on an initial patch by Karim Raslan. Signed-off-by: Karim Allah Ahmed <karim.allah.ahmed@gmail.com> Signed-off-by: Thomas Leonard <talex5@gmail.com> Acked-by: Ian Campbell <ian.campbell@citrix.com>
This commit is contained in:
Thomas Leonard authored and Ian Campbell committed
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4 files changed
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@@ -0,0 +1,211 @@
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@ Offset of the kernel within the RAM. This is a Linux/zImage convention which we
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@ rely on for now.
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#define ZIMAGE_KERNEL_OFFSET 0x8000
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.section .text
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.globl _start
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_start:
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@ zImage header
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.rept 8
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mov r0, r0
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.endr
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b reset
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.word 0x016f2818 @ Magic numbers to help the loader
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.word 0 @ zImage start address (0 = relocatable)
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.word _edata - _start @ zImage end address (excludes bss section)
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@ end of zImage header
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@ Called at boot time. Sets up MMU, exception vectors and stack, and then calls C arch_init() function.
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@ => r2 -> DTB
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@ <= never returns
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@ Note: this boot code needs to be within the first (1MB - ZIMAGE_KERNEL_OFFSET) of _start.
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reset:
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@ Problem: the C code wants to be at a known address (_start), but Xen might
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@ load us anywhere. We initialise the MMU (mapping virtual to physical @ addresses)
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@ so everything ends up where the code expects it to be.
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@
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@ We calculate the offet between where the linker thought _start would be and where
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@ it actually is and initialise the page tables to have that offset for every page.
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@
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@ When we turn on the MMU, we're still executing at the old address. We don't want
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@ the code to disappear from under us. So we have to do the mapping in stages:
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@
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@ 1. set up a mapping to our current page from both its current and desired addresses
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@ 2. enable the MMU
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@ 3. jump to the new address
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@ 4. remap all the other pages with the calculated offset
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adr r1, _start @ r1 = physical address of _start
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ldr r3, =_start @ r3 = (desired) virtual address of _start
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sub r9, r1, r3 @ r9 = (physical - virtual) offset
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ldr r7, =_page_dir @ r7 = (desired) virtual addr of translation table
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add r1, r7, r9 @ r1 = physical addr of translation table
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@ Tell the system where our page table is located.
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@ This is the 16 KB top-level translation table, in which
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@ each word maps one 1MB virtual section to a physical section.
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@ Note: We leave TTBCR as 0, meaning that only TTBR0 is used and
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@ we use the short-descriptor format (32-bit physical addresses).
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orr r0, r1, #0b0001011 @ Sharable, Inner/Outer Write-Back Write-Allocate Cacheable
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mcr p15, 0, r0, c2, c0, 0 @ set TTBR0
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@ Set access permission for domains.
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@ Domains are deprecated, but we have to configure them anyway.
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@ We mark every page as being domain 0 and set domain 0 to "client mode"
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@ (client mode = use access flags in page table).
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mov r0, #1 @ 1 = client
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mcr p15, 0, r0, c3, c0, 0 @ DACR
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@ Template (flags) for a 1 MB page-table entry.
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@ TEX[2:0] C B = 001 1 1 (outer and inner write-back, write-allocate)
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ldr r8, =(0x2 + /* Section entry */ \
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0xc + /* C B */ \
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(3 << 10) + /* Read/write */ \
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(1 << 12) + /* TEX */ \
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(1 << 16) + /* Sharable */ \
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(1<<19)) /* Non-secure */
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@ r8 = template page table entry
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@ Add an entry for the current physical section, at the old and new
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@ addresses. It's OK if they're the same.
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mov r0, pc, lsr#20
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mov r0, r0, lsl#20 @ r0 = physical address of this code's section start
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orr r3, r0, r8 @ r3 = table entry for this section
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ldr r4, =_start @ r4 = desired virtual address of this section
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str r3, [r1, r4, lsr#18] @ map desired virtual section to this code
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str r3, [r1, r0, lsr#18] @ map current section to this code too
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@ Invalidate TLB
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dsb @ Caching is off, but must still prevent reordering
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mcr p15, 0, r1, c8, c7, 0 @ TLBIALL
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@ Enable MMU / SCTLR
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mrc p15, 0, r1, c1, c0, 0 @ SCTLR
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orr r1, r1, #3 << 11 @ enable icache, branch prediction
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orr r1, r1, #4 + 1 @ enable dcache, MMU
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mcr p15, 0, r1, c1, c0, 0 @ SCTLR
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isb
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ldr r1, =stage2 @ Virtual address of stage2
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bx r1
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@ Called once the MMU is enabled. The boot code and the page table are mapped,
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@ but nothing else is yet.
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@
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@ => r2 -> dtb (physical)
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@ r7 = virtual address of page table
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@ r8 = section entry template (flags)
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@ r9 = desired physical - virtual offset
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@ pc -> somewhere in newly-mapped virtual code section
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stage2:
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@ Invalidate TLB
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mcr p15, 0, r1, c8, c7, 0 @ TLBIALL
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isb
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@ The new mapping has now taken effect:
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@ r7 -> page_dir
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@ Fill in the whole top-level translation table (at page_dir).
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@ Populate the whole pagedir with 1MB section descriptors.
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mov r1, r7 @ r1 -> first section entry
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add r3, r1, #4*4*1024 @ limit (4 GB address space, 4 byte entries)
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orr r0, r8, r9 @ r0 = entry mapping section zero to start of physical RAM
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1:
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str r0, [r1],#4 @ write the section entry
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add r0, r0, #1 << 20 @ next physical page (wraps)
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cmp r1, r3
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bne 1b
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@ Invalidate TLB
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dsb
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mcr p15, 0, r1, c8, c7, 0 @ TLBIALL
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isb
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@ Set VBAR -> exception_vector_table
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@ SCTLR.V = 0
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adr r0, exception_vector_table
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mcr p15, 0, r0, c12, c0, 0
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@ Enable hardware floating point:
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@ 1. Access to CP10 and CP11 must be enabled in the Coprocessor Access
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@ Control Register (CP15.CACR):
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mrc p15, 0, r1, c1, c0, 2 @ CACR
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orr r1, r1, #(3 << 20) + (3 << 22) @ full access for CP10 & CP11
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mcr p15, 0, r1, c1, c0, 2
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@ 2. The EN bit in the FPEXC register must be set:
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vmrs r0, FPEXC
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orr r0, r0, #1<<30 @ EN (enable)
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vmsr FPEXC, r0
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@ Initialise 16 KB stack
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ldr sp, =_boot_stack_end
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sub r0, r2, r9 @ r0 -> device tree (virtual address)
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mov r1, r9 @ r1 = physical_address_offset
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b arch_init
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.pushsection .bss
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@ Note: calling arch_init zeroes out this region.
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.align 12
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.globl shared_info_page
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shared_info_page:
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.fill (1024), 4, 0x0
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.align 3
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.globl irqstack
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.globl irqstack_end
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irqstack:
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.fill (1024), 4, 0x0
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irqstack_end:
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.popsection
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@ exception base address
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.align 5
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.globl exception_vector_table
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@ Note: remember to call CLREX if returning from an exception:
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@ "The architecture enables the local monitor to treat any exclusive store as
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@ matching a previous LDREX address. For this reason, use of the CLREX
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@ instruction to clear an existing tag is required on context switches."
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@ -- ARM Cortex-A Series Programmer’s Guide (Version: 4.0)
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exception_vector_table:
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b . @ reset
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b . @ undefined instruction
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b . @ supervisor call
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b . @ prefetch call
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b . @ prefetch abort
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b . @ data abort
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b irq_handler @ irq
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.word 0xe7f000f0 @ abort on FIQ
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@ Call fault_undefined_instruction in "Undefined mode"
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bug:
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.word 0xe7f000f0 @ und/udf - a "Permanently Undefined" instruction
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irq_handler:
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ldr sp, =irqstack_end
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push {r0 - r12, r14}
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ldr r0, IRQ_handler
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cmp r0, #0
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beq bug
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blx r0 @ call handler
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@ Return from IRQ
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pop {r0 - r12, r14}
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clrex
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subs pc, lr, #4
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.globl IRQ_handler
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IRQ_handler:
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.long 0x0
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@ This is called if you try to divide by zero. For now, we make a supervisor call,
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@ which will make us halt.
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.globl raise
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raise:
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svc 0
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@@ -0,0 +1,64 @@
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/******************************************************************************
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* hypercall.S
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*
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* Xen hypercall wrappers
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*
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* Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Citrix, 2012
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation; or, when distributed
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* separately from the Linux kernel or incorporated into other
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* software packages, subject to the following license:
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this source file (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy, modify,
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* merge, publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <xen/xen.h>
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#define __HVC(imm16) .long ((0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F)) & 0xFFFFFFFF)
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#define XEN_IMM 0xEA1
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#define HYPERCALL_SIMPLE(hypercall) \
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.globl HYPERVISOR_##hypercall; \
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.align 4,0x90; \
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HYPERVISOR_##hypercall: \
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mov r12, #__HYPERVISOR_##hypercall; \
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__HVC(XEN_IMM); \
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mov pc, lr;
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#define _hypercall0 HYPERCALL_SIMPLE
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#define _hypercall1 HYPERCALL_SIMPLE
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#define _hypercall2 HYPERCALL_SIMPLE
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#define _hypercall3 HYPERCALL_SIMPLE
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#define _hypercall4 HYPERCALL_SIMPLE
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_hypercall2(sched_op);
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_hypercall2(memory_op);
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_hypercall2(event_channel_op);
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_hypercall2(xen_version);
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_hypercall3(console_io);
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_hypercall1(physdev_op);
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_hypercall3(grant_table_op);
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_hypercall3(vcpu_op);
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_hypercall1(sysctl);
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_hypercall1(domctl);
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_hypercall2(hvm_op);
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_hypercall1(xsm_op);
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Executable
+83
@@ -0,0 +1,83 @@
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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SECTIONS
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{
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/* Note: we currently assume that Xen will load the kernel image
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* at start-of-RAM + 0x8000. We use this initial 32 KB for the stack
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* and translation tables.
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*/
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_boot_stack = 0x400000; /* 16 KB boot stack */
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_boot_stack_end = 0x404000;
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_page_dir = 0x404000; /* 16 KB translation table */
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. = 0x408000;
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_text = .; /* Text and read-only data */
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.text : {
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*(.text)
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*(.gnu.warning)
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} = 0x9090
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_etext = .; /* End of text section */
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.rodata : { *(.rodata) *(.rodata.*) }
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. = ALIGN(4096);
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_erodata = .;
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/* newlib initialization functions */
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. = ALIGN(32 / 8);
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PROVIDE (__preinit_array_start = .);
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.preinit_array : { *(.preinit_array) }
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PROVIDE (__preinit_array_end = .);
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PROVIDE (__init_array_start = .);
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.init_array : { *(.init_array) }
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PROVIDE (__init_array_end = .);
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PROVIDE (__fini_array_start = .);
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.fini_array : { *(.fini_array) }
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PROVIDE (__fini_array_end = .);
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.ctors : {
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__CTOR_LIST__ = .;
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*(.ctors)
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CONSTRUCTORS
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LONG(0)
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__CTOR_END__ = .;
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}
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.dtors : {
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__DTOR_LIST__ = .;
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*(.dtors)
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LONG(0)
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__DTOR_END__ = .;
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}
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|
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.data : { /* Data */
|
||||
*(.data)
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}
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||||
|
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/* Note: linker will insert any extra sections here, just before .bss */
|
||||
|
||||
.bss : {
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||||
_edata = .; /* End of data included in image */
|
||||
/* Nothing after here is included in the zImage's size */
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||||
|
||||
__bss_start = .;
|
||||
*(.bss)
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||||
*(.app.bss)
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||||
}
|
||||
_end = . ;
|
||||
|
||||
/* Sections to be discarded */
|
||||
/DISCARD/ : {
|
||||
*(.text.exit)
|
||||
*(.data.exit)
|
||||
*(.exitcall.exit)
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||||
}
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
}
|
||||
@@ -0,0 +1,119 @@
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#include <mini-os/os.h>
|
||||
#include <mini-os/kernel.h>
|
||||
#include <mini-os/gic.h>
|
||||
#include <mini-os/console.h>
|
||||
#include <xen/xen.h>
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||||
#include <xen/memory.h>
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||||
#include <xen/hvm/params.h>
|
||||
#include <arch_mm.h>
|
||||
#include <libfdt.h>
|
||||
|
||||
/*
|
||||
* This structure contains start-of-day info, such as pagetable base pointer,
|
||||
* address of the shared_info structure, and things like that.
|
||||
* On x86, the hypervisor passes it to us. On ARM, we fill it in ourselves.
|
||||
*/
|
||||
union start_info_union start_info_union;
|
||||
|
||||
/*
|
||||
* Shared page for communicating with the hypervisor.
|
||||
* Events flags go here, for example.
|
||||
*/
|
||||
shared_info_t *HYPERVISOR_shared_info;
|
||||
|
||||
extern char shared_info_page[PAGE_SIZE];
|
||||
|
||||
void *device_tree;
|
||||
|
||||
static int hvm_get_parameter(int idx, uint64_t *value)
|
||||
{
|
||||
struct xen_hvm_param xhv;
|
||||
int ret;
|
||||
|
||||
xhv.domid = DOMID_SELF;
|
||||
xhv.index = idx;
|
||||
ret = HYPERVISOR_hvm_op(HVMOP_get_param, &xhv);
|
||||
if (ret < 0) {
|
||||
BUG();
|
||||
}
|
||||
*value = xhv.value;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void get_console(void)
|
||||
{
|
||||
uint64_t v = -1;
|
||||
|
||||
hvm_get_parameter(HVM_PARAM_CONSOLE_EVTCHN, &v);
|
||||
start_info.console.domU.evtchn = v;
|
||||
|
||||
hvm_get_parameter(HVM_PARAM_CONSOLE_PFN, &v);
|
||||
start_info.console.domU.mfn = v;
|
||||
|
||||
printk("Console is on port %d\n", start_info.console.domU.evtchn);
|
||||
printk("Console ring is at mfn %lx\n", (unsigned long) start_info.console.domU.mfn);
|
||||
}
|
||||
|
||||
void get_xenbus(void)
|
||||
{
|
||||
uint64_t value;
|
||||
|
||||
if (hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &value))
|
||||
BUG();
|
||||
|
||||
start_info.store_evtchn = (int)value;
|
||||
|
||||
if(hvm_get_parameter(HVM_PARAM_STORE_PFN, &value))
|
||||
BUG();
|
||||
start_info.store_mfn = (unsigned long)value;
|
||||
}
|
||||
|
||||
/*
|
||||
* INITIAL C ENTRY POINT.
|
||||
*/
|
||||
void arch_init(void *dtb_pointer, uint32_t physical_offset)
|
||||
{
|
||||
struct xen_add_to_physmap xatp;
|
||||
int r;
|
||||
|
||||
memset(&__bss_start, 0, &_end - &__bss_start);
|
||||
|
||||
physical_address_offset = physical_offset;
|
||||
|
||||
xprintk("Virtual -> physical offset = %x\n", physical_address_offset);
|
||||
|
||||
xprintk("Checking DTB at %p...\n", dtb_pointer);
|
||||
|
||||
if ((r = fdt_check_header(dtb_pointer))) {
|
||||
xprintk("Invalid DTB from Xen: %s\n", fdt_strerror(r));
|
||||
BUG();
|
||||
}
|
||||
device_tree = dtb_pointer;
|
||||
|
||||
/* Map shared_info page */
|
||||
xatp.domid = DOMID_SELF;
|
||||
xatp.idx = 0;
|
||||
xatp.space = XENMAPSPACE_shared_info;
|
||||
xatp.gpfn = virt_to_pfn(shared_info_page);
|
||||
if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp) != 0)
|
||||
BUG();
|
||||
HYPERVISOR_shared_info = (struct shared_info *)shared_info_page;
|
||||
|
||||
/* Fill in start_info */
|
||||
get_console();
|
||||
get_xenbus();
|
||||
|
||||
gic_init();
|
||||
|
||||
start_kernel();
|
||||
}
|
||||
|
||||
void
|
||||
arch_fini(void)
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
arch_do_exit(void)
|
||||
{
|
||||
}
|
||||