xen/arm: Place a speculation barrier sequence following an eret instruction

Some CPUs can speculate past an ERET instruction and potentially perform
speculative accesses to memory before processing the exception return.
Since the register state is often controlled by lower privilege level
at the point of an ERET, this could potentially be used as part of a
side-channel attack.

Newer CPUs may implement a new SB barrier instruction which acts
as an architected speculation barrier. For current CPUs, the sequence
DSB; ISB is known to prevent speculation.

The latter sequence is heavier than SB but it would never be executed
(this is speculation after all!).

Introduce a new macro 'sb' that could be used when a speculation barrier
is required. For now it is using dsb; isb but this could easily be
updated to cater SB in the future.

This is XSA-312.

Signed-off-by: Julien Grall <julien@xen.org>
This commit is contained in:
Julien Grall committed 2020-01-14 14:26:14 +00:00
1 parent 14b62ab3e5
commit ddffc4d8a0
3 files changed
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@@ -1,4 +1,5 @@
#include <asm/asm_defns.h>
#include <asm/macros.h>
#include <asm/regs.h>
#include <asm/alternative.h>
#include <public/xen.h>
@@ -379,6 +380,7 @@ return_to_hypervisor:
add sp, #(UREGS_SP_usr - UREGS_sp); /* SP, LR, SPSR, PC */
clrex
eret
sb
/*
* struct vcpu *__context_switch(struct vcpu *prev, struct vcpu *next)
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@@ -2,6 +2,7 @@
#include <asm/regs.h>
#include <asm/alternative.h>
#include <asm/smccc.h>
#include <asm/macros.h>
#include <public/xen.h>
/*
@@ -288,6 +289,7 @@ guest_sync:
*/
mov x1, xzr
eret
sb
1:
/*
@@ -413,6 +415,7 @@ return_from_trap:
ldr lr, [sp], #(UREGS_SPSR_el1 - UREGS_LR) /* CPSR, PC, SP, LR */
eret
sb
/*
* This function is used to check pending virtual SError in the gap of
+9
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@@ -13,4 +13,13 @@
# error "unknown ARM variant"
#endif
/*
* Speculative barrier
* XXX: Add support for the 'sb' instruction
*/
.macro sb
dsb nsh
isb
.endm
#endif /* __ASM_ARM_MACROS_H */
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