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xen/arm: Place a speculation barrier sequence following an eret instruction
Some CPUs can speculate past an ERET instruction and potentially perform speculative accesses to memory before processing the exception return. Since the register state is often controlled by lower privilege level at the point of an ERET, this could potentially be used as part of a side-channel attack. Newer CPUs may implement a new SB barrier instruction which acts as an architected speculation barrier. For current CPUs, the sequence DSB; ISB is known to prevent speculation. The latter sequence is heavier than SB but it would never be executed (this is speculation after all!). Introduce a new macro 'sb' that could be used when a speculation barrier is required. For now it is using dsb; isb but this could easily be updated to cater SB in the future. This is XSA-312. Signed-off-by: Julien Grall <julien@xen.org>
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@@ -1,4 +1,5 @@
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#include <asm/asm_defns.h>
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#include <asm/macros.h>
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#include <asm/regs.h>
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#include <asm/alternative.h>
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#include <public/xen.h>
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@@ -379,6 +380,7 @@ return_to_hypervisor:
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add sp, #(UREGS_SP_usr - UREGS_sp); /* SP, LR, SPSR, PC */
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clrex
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eret
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sb
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/*
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* struct vcpu *__context_switch(struct vcpu *prev, struct vcpu *next)
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@@ -2,6 +2,7 @@
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#include <asm/regs.h>
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#include <asm/alternative.h>
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#include <asm/smccc.h>
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#include <asm/macros.h>
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#include <public/xen.h>
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/*
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@@ -288,6 +289,7 @@ guest_sync:
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*/
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mov x1, xzr
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eret
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sb
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1:
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/*
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@@ -413,6 +415,7 @@ return_from_trap:
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ldr lr, [sp], #(UREGS_SPSR_el1 - UREGS_LR) /* CPSR, PC, SP, LR */
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eret
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sb
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/*
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* This function is used to check pending virtual SError in the gap of
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@@ -13,4 +13,13 @@
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# error "unknown ARM variant"
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#endif
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/*
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* Speculative barrier
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* XXX: Add support for the 'sb' instruction
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*/
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.macro sb
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dsb nsh
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isb
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.endm
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#endif /* __ASM_ARM_MACROS_H */
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