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x86/hvm: Expose Automatic IBRS to guests
Expose AutoIBRS to HVM guests. EFER is swapped by VMRUN, so Xen only has to make sure writes to EFER.AIBRSE are gated on the feature being exposed. Hide EFER.AIBRSE from PV guests. Xen currently has no concept of per-PV-guest EFER settings. Signed-off-by: Alejandro Vallejo <alejandro.vallejo@cloud.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
This commit is contained in:
Alejandro Vallejo authored and Andrew Cooper committed
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8347d6bb29
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4 files changed
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@@ -936,6 +936,9 @@ const char *hvm_efer_valid(const struct vcpu *v, uint64_t value,
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if ( (value & EFER_FFXSE) && !p->extd.ffxsr )
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return "FFXSE without feature";
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if ( (value & EFER_AIBRSE) && !p->extd.auto_ibrs )
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return "AutoIBRS without feature";
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return NULL;
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}
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@@ -178,7 +178,8 @@
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#define EFER_AIBRSE (_AC(1, ULL) << 21) /* Automatic IBRS Enable */
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#define EFER_KNOWN_MASK \
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(EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE)
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(EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE | \
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EFER_AIBRSE)
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#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
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#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
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@@ -853,8 +853,8 @@ static uint64_t guest_efer(const struct domain *d)
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{
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uint64_t val;
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/* Hide unknown bits, and unconditionally hide SVME from guests. */
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val = read_efer() & EFER_KNOWN_MASK & ~EFER_SVME;
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/* Hide unknown bits, and unconditionally hide SVME and AIBRSE from guests. */
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val = read_efer() & EFER_KNOWN_MASK & ~(EFER_SVME | EFER_AIBRSE);
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/*
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* Hide the 64-bit features from 32-bit guests. SCE has
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* vendor-dependent behaviour.
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@@ -287,7 +287,7 @@ XEN_CPUFEATURE(AVX_IFMA, 10*32+23) /*A AVX-IFMA Instructions */
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/* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */
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XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE always serializing */
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XEN_CPUFEATURE(NSCB, 11*32+ 6) /*A Null Selector Clears Base (and limit too) */
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XEN_CPUFEATURE(AUTO_IBRS, 11*32+ 8) /* Automatic IBRS */
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XEN_CPUFEATURE(AUTO_IBRS, 11*32+ 8) /*S Automatic IBRS */
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XEN_CPUFEATURE(CPUID_USER_DIS, 11*32+17) /* CPUID disable for CPL > 0 software */
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/* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */
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