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x86,arm: remove asm/spinlock.h from all architectures
Now that all architecture use a common ticket lock implementation for spinlocks, remove the architecture specific byte lock implementations. Signed-off-by: David Vrabel <david.vrabel@citrix.com> Reviewed-by: Tim Deegan <tim@xen.org> Acked-by: Jan Beulich <jbeulich@suse.com> Acked-by: Ian Campbell <ian.campbell@citrix.com>
This commit is contained in:
David Vrabel authored and 
Jan Beulich committed
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@@ -25,16 +25,6 @@ linux/arch/arm64/include/asm/atomic.h xen/include/asm-arm/arm64/atomic.h
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---------------------------------------------------------------------
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spinlocks: last sync @ v3.16-rc6 (last commit: 95c4189689f9)
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linux/arch/arm64/include/asm/spinlock.h xen/include/asm-arm/arm64/spinlock.h
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Skipped:
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5686b06 arm64: lockref: add support for lockless lockrefs using cmpxchg
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52ea2a5 arm64: locks: introduce ticket-based spinlock implementation
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---------------------------------------------------------------------
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mem*: last sync @ v3.16-rc6 (last commit: d875c9b37240)
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linux/arch/arm64/lib/memchr.S xen/arch/arm/arm64/lib/memchr.S
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@@ -103,24 +93,6 @@ linux/arch/arm/include/asm/atomic.h xen/include/asm-arm/arm32/atomic.h
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---------------------------------------------------------------------
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spinlocks: last sync: 15e7e5c1ebf5
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linux/arch/arm/include/asm/spinlock.h xen/include/asm-arm/arm32/spinlock.h
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*** Linux has switched to ticket locks but we still use bitlocks.
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resync to v3.14-rc7:
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7c8746a ARM: 7955/1: spinlock: ensure we have a compiler barrier before sev
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0cbad9c ARM: 7854/1: lockref: add support for lockless lockrefs using cmpxchg64
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9bb17be ARM: locks: prefetch the destination word for write prior to strex
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27a8479 ARM: smp_on_up: move inline asm ALT_SMP patching macro out of spinlock.
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00efaa0 ARM: 7812/1: rwlocks: retry trylock operation if strex fails on free lo
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afa31d8 ARM: 7811/1: locks: use early clobber in arch_spin_trylock
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73a6fdc ARM: spinlock: use inner-shareable dsb variant prior to sev instruction
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---------------------------------------------------------------------
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mem*: last sync @ v3.16-rc6 (last commit: d98b90ea22b0)
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linux/arch/arm/lib/copy_template.S xen/arch/arm/arm32/lib/copy_template.S
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@@ -1,66 +0,0 @@
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#ifndef __ASM_ARM32_SPINLOCK_H
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#define __ASM_ARM32_SPINLOCK_H
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static inline void dsb_sev(void)
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{
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__asm__ __volatile__ (
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"dsb\n"
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"sev\n"
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);
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}
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typedef struct {
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volatile unsigned int lock;
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} raw_spinlock_t;
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#define _RAW_SPIN_LOCK_UNLOCKED { 0 }
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#define _raw_spin_is_locked(x) ((x)->lock != 0)
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static always_inline void _raw_spin_unlock(raw_spinlock_t *lock)
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{
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ASSERT(_raw_spin_is_locked(lock));
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smp_mb();
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__asm__ __volatile__(
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" str %1, [%0]\n"
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:
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: "r" (&lock->lock), "r" (0)
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: "cc");
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dsb_sev();
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}
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static always_inline int _raw_spin_trylock(raw_spinlock_t *lock)
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{
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unsigned long contended, res;
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do {
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__asm__ __volatile__(
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" ldrex %0, [%2]\n"
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" teq %0, #0\n"
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" strexeq %1, %3, [%2]\n"
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" movne %1, #0\n"
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: "=&r" (contended), "=r" (res)
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: "r" (&lock->lock), "r" (1)
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: "cc");
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} while (res);
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if (!contended) {
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smp_mb();
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return 1;
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} else {
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return 0;
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}
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}
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#endif /* __ASM_SPINLOCK_H */
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/*
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* Local variables:
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* mode: C
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* c-file-style: "BSD"
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* c-basic-offset: 4
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* indent-tabs-mode: nil
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* End:
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*/
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@@ -1,63 +0,0 @@
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/*
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* Derived from Linux arch64 spinlock.h which is:
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ARM64_SPINLOCK_H
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#define __ASM_ARM64_SPINLOCK_H
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typedef struct {
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volatile unsigned int lock;
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} raw_spinlock_t;
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#define _RAW_SPIN_LOCK_UNLOCKED { 0 }
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#define _raw_spin_is_locked(x) ((x)->lock != 0)
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static always_inline void _raw_spin_unlock(raw_spinlock_t *lock)
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{
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ASSERT(_raw_spin_is_locked(lock));
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asm volatile(
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" stlr %w1, %0\n"
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: "=Q" (lock->lock) : "r" (0) : "memory");
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}
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static always_inline int _raw_spin_trylock(raw_spinlock_t *lock)
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{
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unsigned int tmp;
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asm volatile(
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"2: ldaxr %w0, %1\n"
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" cbnz %w0, 1f\n"
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" stxr %w0, %w2, %1\n"
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" cbnz %w0, 2b\n"
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"1:\n"
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: "=&r" (tmp), "+Q" (lock->lock)
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: "r" (1)
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: "cc", "memory");
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return !tmp;
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}
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#endif /* __ASM_SPINLOCK_H */
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/*
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* Local variables:
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* mode: C
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* c-file-style: "BSD"
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* c-basic-offset: 4
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* indent-tabs-mode: nil
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* End:
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*/
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@@ -1,23 +0,0 @@
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#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <xen/config.h>
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#include <xen/lib.h>
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#if defined(CONFIG_ARM_32)
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# include <asm/arm32/spinlock.h>
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#elif defined(CONFIG_ARM_64)
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# include <asm/arm64/spinlock.h>
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#else
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# error "unknown ARM variant"
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#endif
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#endif /* __ASM_SPINLOCK_H */
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/*
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* Local variables:
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* mode: C
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* c-file-style: "BSD"
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* c-basic-offset: 4
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* indent-tabs-mode: nil
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* End:
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*/
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@@ -1,37 +0,0 @@
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#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <xen/config.h>
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#include <xen/lib.h>
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#include <asm/atomic.h>
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typedef struct {
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volatile s16 lock;
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} raw_spinlock_t;
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#define _RAW_SPIN_LOCK_UNLOCKED /*(raw_spinlock_t)*/ { 1 }
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#define _raw_spin_is_locked(x) ((x)->lock <= 0)
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static always_inline void _raw_spin_unlock(raw_spinlock_t *lock)
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{
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ASSERT(_raw_spin_is_locked(lock));
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asm volatile (
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"movw $1,%0"
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: "=m" (lock->lock) : : "memory" );
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}
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static always_inline int _raw_spin_trylock(raw_spinlock_t *lock)
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{
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s16 oldval;
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asm volatile (
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"xchgw %w0,%1"
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:"=r" (oldval), "=m" (lock->lock)
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:"0" ((s16)0) : "memory" );
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return (oldval > 0);
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}
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#define _raw_read_unlock(l) \
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asm volatile ( "lock; dec%z0 %0" : "+m" ((l)->lock) :: "memory" )
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#endif /* __ASM_SPINLOCK_H */
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@@ -2,7 +2,6 @@
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#define __SPINLOCK_H__
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#include <asm/system.h>
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#include <asm/spinlock.h>
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#ifndef NDEBUG
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struct lock_debug {
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