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xen: enable APIC-Register Virtualization
Add APIC register virtualization support - APIC read doesn't cause VM-Exit - APIC write becomes trap-like Signed-off-by: Gang Wei <gang.wei@intel.com> Signed-off-by: Yang Zhang <yang.z.zhang@intel.com> Signed-off-by: Jiongxi Li <jiongxi.li@intel.com>
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@@ -823,6 +823,14 @@ static int vlapic_write(struct vcpu *v, unsigned long address,
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return rc;
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}
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int vlapic_apicv_write(struct vcpu *v, unsigned int offset)
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{
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uint32_t val = vlapic_get_reg(vcpu_vlapic(v), offset);
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vlapic_reg_write(v, offset, val);
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return 0;
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}
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int hvm_x2apic_msr_write(struct vcpu *v, unsigned int msr, uint64_t msr_content)
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{
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struct vlapic *vlapic = vcpu_vlapic(v);
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@@ -89,6 +89,7 @@ static void __init vmx_display_features(void)
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P(cpu_has_vmx_vnmi, "Virtual NMI");
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P(cpu_has_vmx_msr_bitmap, "MSR direct-access bitmap");
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P(cpu_has_vmx_unrestricted_guest, "Unrestricted Guest");
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P(cpu_has_vmx_apic_reg_virt, "APIC Register Virtualization");
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#undef P
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if ( !printed )
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@@ -182,6 +183,14 @@ static int vmx_init_vmcs_config(void)
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if ( opt_unrestricted_guest_enabled )
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opt |= SECONDARY_EXEC_UNRESTRICTED_GUEST;
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/*
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* "APIC Register Virtualization"
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* can be set only when "use TPR shadow" is set
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*/
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if ( _vmx_cpu_based_exec_control & CPU_BASED_TPR_SHADOW )
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opt |= SECONDARY_EXEC_APIC_REGISTER_VIRT;
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_vmx_secondary_exec_control = adjust_vmx_controls(
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"Secondary Exec Control", min, opt,
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MSR_IA32_VMX_PROCBASED_CTLS2, &mismatch);
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@@ -2197,6 +2197,16 @@ static void vmx_idtv_reinject(unsigned long idtv_info)
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}
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}
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static int vmx_handle_apic_write(void)
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{
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unsigned long exit_qualification = __vmread(EXIT_QUALIFICATION);
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unsigned int offset = exit_qualification & 0xfff;
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ASSERT(cpu_has_vmx_apic_reg_virt);
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return vlapic_apicv_write(current, offset);
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}
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void vmx_vmexit_handler(struct cpu_user_regs *regs)
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{
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unsigned int exit_reason, idtv_info, intr_info = 0, vector = 0;
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@@ -2649,6 +2659,11 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs)
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break;
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}
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case EXIT_REASON_APIC_WRITE:
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if ( vmx_handle_apic_write() )
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hvm_inject_hw_exception(TRAP_gp_fault, 0);
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break;
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case EXIT_REASON_ACCESS_GDTR_OR_IDTR:
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case EXIT_REASON_ACCESS_LDTR_OR_TR:
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case EXIT_REASON_VMX_PREEMPTION_TIMER_EXPIRED:
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@@ -103,6 +103,8 @@ void vlapic_EOI_set(struct vlapic *vlapic);
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int vlapic_ipi(struct vlapic *vlapic, uint32_t icr_low, uint32_t icr_high);
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int vlapic_apicv_write(struct vcpu *v, unsigned int offset);
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struct vlapic *vlapic_lowest_prio(
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struct domain *d, struct vlapic *source,
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int short_hand, uint8_t dest, uint8_t dest_mode);
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@@ -180,6 +180,7 @@ extern u32 vmx_vmentry_control;
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#define SECONDARY_EXEC_ENABLE_VPID 0x00000020
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#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
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#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
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#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
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#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
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#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
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extern u32 vmx_secondary_exec_control;
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@@ -228,6 +229,8 @@ extern bool_t cpu_has_vmx_ins_outs_instr_info;
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SECONDARY_EXEC_UNRESTRICTED_GUEST)
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#define cpu_has_vmx_ple \
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(vmx_secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
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#define cpu_has_vmx_apic_reg_virt \
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(vmx_secondary_exec_control & SECONDARY_EXEC_APIC_REGISTER_VIRT)
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/* GUEST_INTERRUPTIBILITY_INFO flags. */
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#define VMX_INTR_SHADOW_STI 0x00000001
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@@ -129,6 +129,7 @@ void vmx_update_cpu_exec_control(struct vcpu *v);
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#define EXIT_REASON_INVVPID 53
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#define EXIT_REASON_WBINVD 54
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#define EXIT_REASON_XSETBV 55
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#define EXIT_REASON_APIC_WRITE 56
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#define EXIT_REASON_INVPCID 58
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/*
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