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x86emul: support SHA insns
Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
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Jan Beulich committed
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2 files changed
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@@ -373,6 +373,7 @@ static const struct {
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[0x37 ... 0x3f] = { .simd_size = simd_packed_int },
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[0x40] = { .simd_size = simd_packed_int },
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[0x41] = { .simd_size = simd_packed_int, .two_op = 1 },
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[0xc8 ... 0xcd] = { .simd_size = simd_other },
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[0xdb] = { .simd_size = simd_packed_int, .two_op = 1 },
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[0xdc ... 0xdf] = { .simd_size = simd_packed_int },
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[0xf0] = { .two_op = 1 },
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@@ -404,6 +405,7 @@ static const struct {
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[0x4a ... 0x4b] = { .simd_size = simd_packed_fp, .four_op = 1 },
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[0x4c] = { .simd_size = simd_packed_int, .four_op = 1 },
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[0x60 ... 0x63] = { .simd_size = simd_packed_int, .two_op = 1 },
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[0xcc] = { .simd_size = simd_other },
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[0xdf] = { .simd_size = simd_packed_int, .two_op = 1 },
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[0xf0] = {},
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};
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@@ -1500,6 +1502,7 @@ static bool vcpu_has(
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#define vcpu_has_smap() vcpu_has( 7, EBX, 20, ctxt, ops)
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#define vcpu_has_clflushopt() vcpu_has( 7, EBX, 23, ctxt, ops)
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#define vcpu_has_clwb() vcpu_has( 7, EBX, 24, ctxt, ops)
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#define vcpu_has_sha() vcpu_has( 7, EBX, 29, ctxt, ops)
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#define vcpu_has_rdpid() vcpu_has( 7, ECX, 22, ctxt, ops)
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#define vcpu_must_have(feat) \
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@@ -7187,6 +7190,16 @@ x86_emulate(
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host_and_vcpu_must_have(sse4_2);
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goto simd_0f38_common;
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case X86EMUL_OPC(0x0f38, 0xc8): /* sha1nexte xmm/m128,xmm */
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case X86EMUL_OPC(0x0f38, 0xc9): /* sha1msg1 xmm/m128,xmm */
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case X86EMUL_OPC(0x0f38, 0xca): /* sha1msg2 xmm/m128,xmm */
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case X86EMUL_OPC(0x0f38, 0xcb): /* sha256rnds2 XMM0,xmm/m128,xmm */
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case X86EMUL_OPC(0x0f38, 0xcc): /* sha256msg1 xmm/m128,xmm */
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case X86EMUL_OPC(0x0f38, 0xcd): /* sha256msg2 xmm/m128,xmm */
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host_and_vcpu_must_have(sha);
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op_bytes = 16;
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goto simd_0f38_common;
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case X86EMUL_OPC_66(0x0f38, 0xdb): /* aesimc xmm/m128,xmm */
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case X86EMUL_OPC_VEX_66(0x0f38, 0xdb): /* vaesimc xmm/m128,xmm */
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case X86EMUL_OPC_66(0x0f38, 0xdc): /* aesenc xmm/m128,xmm,xmm */
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@@ -7571,6 +7584,11 @@ x86_emulate(
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dst.type = OP_NONE;
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break;
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case X86EMUL_OPC(0x0f3a, 0xcc): /* sha1rnds4 $imm8,xmm/m128,xmm */
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host_and_vcpu_must_have(sha);
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op_bytes = 16;
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goto simd_0f3a_common;
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case X86EMUL_OPC_66(0x0f3a, 0xdf): /* aeskeygenassist $imm8,xmm/m128,xmm */
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case X86EMUL_OPC_VEX_66(0x0f3a, 0xdf): /* vaeskeygenassist $imm8,xmm/m128,xmm */
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host_and_vcpu_must_have(aesni);
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@@ -87,6 +87,7 @@
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#define cpu_has_hle boot_cpu_has(X86_FEATURE_HLE)
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#define cpu_has_rtm boot_cpu_has(X86_FEATURE_RTM)
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#define cpu_has_pdcm boot_cpu_has(X86_FEATURE_PDCM)
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#define cpu_has_sha boot_cpu_has(X86_FEATURE_SHA)
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enum _cache_type {
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CACHE_TYPE_NULL = 0,
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