To support this add xc_translate_foreign_address to libxc. This function
walks page tables and translates virtual addresses using a given domain
and vcpu page table.
Signed-off-by: Ian Campbell <Ian.Campbell@XenSource.com>
page refcnts for host mappings as they are already
destroyed by put_page_from_l1e(). Also call
gnttab_release_mappings later (after destroying
page-table references) and from common code rather than
arch/x86.
Also a few other misc gnttab cleanups.
Signed-off-by: Keir Fraser <keir@xensource.com>
mapping created via a grant reference, rather than one
increment for all uses of a single grant reference.
This avoids a nasty situation in put_page_from_l1e()
where we cannot reliably determine whether a mapping was
created via a grant reference and so we must always
decrement the mapped page's reference count.
Signed-off-by: Keir Fraser <keir@xensource.com>
Our IPF machines are the following configurations.
- Total logical cpus = 16
-- 4 sockets
-- 2 cores
-- 2 threads
I changed the setting of BIOS, and invalidated the hyperthread, and I built Xen with NR_CPUS=8.
As a result, it became like attached file xendmesg1.txt.
- Available cpus 3
- Total cpus 8
Next, I built Xen with NR_CPUS=16.
As a result, it became like attached file xendmesg2.txt.
- Available cpus 8
- Total cpus 16
I thought not to match the analysis of the lsapic entry to the value of NR_CPUS.
It is an outline of patch as follows.
1. Count up the lsapic entry by using acpi_table_count_madt()/acpi_table_count_madt_family().
2. Call acpi_parse_lsapic() by using the number of lsapic entries.
3. Count up the available_cpus by using acpi_parse_lsapic(), however NR_CPUS is not exceeded.
Signed-off-by: Masaki Kanno <kanno.masaki@jp.fujitsu.com>
Best Regards,
Kan
the exact one updated by scheduler. Or else easy to think how things get
messed under SMP environment. One phenomenon observed is about softirq.
Exit path on CPU1 checks pending indicator by local_cpu_data, and then
goto do_softirq if pending true. However do_softirq uses cpu_data(cpu)
to query pending bit again. Cpu index is aquired from smp_processor_id,
with thread_info->cpu not cared by scheduler. Finally do_softirq on CPU1
tries to operate percpu data on CPU0 then.
Also disable several prints within critical path, like sending IPI. Due to
slow serial speed, this will slow down overall performance heavily since
event channels among CPUs are in traffic.
This patch is necessary for host SMP.
Signed-off-by Kevin Tian <kevin.tian@intel.com>
instructions to the generic x86 emulator. Also add
preliminary support for 16-bit addressing: decode the
ModR/M byte properly but still need to access and update
implicit memory operands (esp,esi,edi) with correct width.
Work is also needed to support real-mode addressing.
Signed-off-by: Keir Fraser <keir@xensource.com>
VIRQ_NMI. Also simplify x86_32 NMI handling -- there's
no need to greedily consume IO/parity errors in
assembly code as they can be deferred without causing
an interrupt storm (the NMI pin is always edge-triggered
even though the sources are level-asserted).
Signed-off-by: Keir Fraser <keir@xensource.com>
ia64, since there're several different system types like HP-ZX, DIG,
etc. Current Makefile can't meet this need and default one
(xen0_defconfig_ia64) is only for HP-ZX type. Hence, this patch can
append an additional param to configuration file name to differentiate
system types when make.
Signed-off-by Zhang Xiantao <xiantao.zhang@intel.com>
platform, it includes:
1) One fix on xc_vmx_build.c
2) Change ram_size/phys_ram_size in qemu from int to uint64_t
3) One fix on pcnet unsigned short to unsigned long conversion.
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Signed-off-by: Xin Li <xin.b.li@intel.com>
This is primarily useful to allow a privileged domain to determine
its domid, where the preferred method of quering xenstore cannot be
used.
Signed-off-by: joseph.cihula@intel.com
__copy_to_user in the swiotlb sync function. We cannot
immediately exit the sync function as there may be tail work
to do (e.g., kunmap_atomic). In fact, doing nothing is the
right thing to do and is sufficient to avoid compiler
warnings about not checking the __copy_to_user return value.
Signed-off-by: Keir Fraser <keir@xensource.com>
mapped for DMA_BIDIRECTIONAL streaming access by certain
low-level drivers. This causes an unnecessary copy to the
host buffer that previously caused a fatal kernel page fault.
Signed-off-by: Keir Fraser <keir@xensource.com>
for whether e820 list is below 1MB: all bootloaders place
it below 1MB so teh check is ineffective and, in any case,
SYSLINUX has the same issue as GRUB (does not pre-initialize
the memory area that e820 function writes to).
Signed-off-by: Keir Fraser <keir@xensource.com>
Signed-off-by Anthony Xu <anthony.xu@intel.com>
Signed-off-by Kevin Tian <kevin.tian@intel.com>
The reason is that Xen/ia64 will try to pend guest timer interrupt to dom0
within each machine timer interrupt handler. To avoid duplicated delivery,
domain_itm_last recorded domain_itm of last injection. If two are identical,
it means interrupt injected but guest has not set new itm value. Or else
corresponding pending irr bit will be turned on. That works in most cases.
However currently guest linux may try to set itm multiple times within one
handler before turn on psr.i again. Among first few settings, new guest timer
interrupt may be pended. Then once guest linux enables interrupt, a new
timer interrupt will be injected immediately. However this injection may have
itc still smaller than the domain_itm set at the last round of last handle.
In this case, guest linux will set same domain_itm as last again. However
since domain_itm_last already equals to domain_itm at last read ivr, later
no guest timer interrupt can be injected any more since Xen always thinks
an instance already injected without guest's response.
Attahced patch fixed this issue by adding sanity check upon guest timer
vector when deciding to inject interrupt into dom0. We always compare current
itc with latest domain_itm that guest really wants. So if itc < domain_itm
at this point, we simply clear the pending bit and no injection.
There's also a small fix to vcpu_read_ivr, where domain_itm_last should
be updated before clearing irr bit. Or els a small window still remains
to add a duplicate interrupt.
