domain builder and in to python code.
This knowledge will be useful to allow us to pre-seed the protocol
field in a VBD entry in xenstore which will allow us to run older
kernels in a 32on64 mixed environment.
Signed-off-by: Ian Campbell <ian.campbell@xensource.com>
ASIDs partition the physical TLB for SVM. In the current implementation
ASIDs are used to reduce the number of TLB flushes. Each time the
guest's virtual address space changes (e.g. due to an INVLPG,
MOV-TO-{CR3, CR4} operation), instead of flushing the TLB, a new ASID is
assigned. This reduces the number of TLB flushes to at most 1/#ASIDs
(currently 1/64). The biggest advantage is that hot parts of the
hypervisor's code and data remain in the TLB.
From: Sebastian Biemueller <Sebastian.Biemueller@amd.com>
Signed-off-by: Keir Fraser <keir@xensource.com>
- make log levels used consistent in a few places
- remove trailing newlines, dots, and commas
- remove explictly specified function names from message text
Signed-off-by: Jan Beulich <jbeulich@novell.com>
CSTAR is an unused MSR in 64-bit mode on Intel's EM64T, hence there's
no need to save/restore this MSR during context switches. Mimic real
hardware by retaining the value written for eventual guest OS reads.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Introduce a per-CPU shadow of what is currently in EFER, as context
switch code must re-write this MSR so that all guests run with
appropriate EFER.SCE and EFER.NX settings. Remove EFER from the set of
MSRs that VMX deals with in a generic fashion.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
- share more code between 32- and 64-bit variants
- properly handle continuations for 32-bit guests on 64-bit hv
- properly handle preemption (this must *not* rely on regs->eip, as
- other code may overwrite the value there by calling
- hvm_store_cpu_guest_regs()
- deny hypercall access when called from guest in vm86 mode, which
requires that ???_guest_x86_mode() make real and vm86 modes distinguishable
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Make sure MFN read from pte is valid before accessing the page info
structure associated with it. Drop guest-to-machine-physical
translation from ptwr code.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Since invalidate_shadow_ldt() depends on process_deferred_ops() to be
called, it shouldn't be visible outside xen/arch/x86/mm.c.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Instead do this only on context switches. In cases where we need
access to state that is only saved to the VMCB on VMSAVE, we track
whether the state is in sync via a per-vcpu flag and VMSAVE on demand.
The context switch code can be further improved:
1. No need to VMLOAD host state if we are switching to another SVM VCPU.
2. No need to VMSAVE host state at all (except once at start of day)
because the registers that are saved do not change (or at least, none
of the ones that matter change).
The performance is improvement is about 650 cycles for a null
hypercall. This reduces the total null-hypercall time for a non-debug
build of Xen down to around 3300 cycles on my AMD X2 system.
Signed-off-by: Keir Fraser <keir@xensource.com>
It turns out that although PIIX4 hardware defines the S5 type code to
be 000, all OSes will discover the correct code by evlauating an \_Sx
object in the ACPI DSDT. And we set the type code in that object to be
111.
So this patch keeps the other cleanups made to the piix4acpi.c file,
but switches back to checking for code 111. It also makes it clearer
in both the ioemu code and in the dsdt source code where these magic
numbers come from.
Let's hope noone actually has the true PIIX4 type codes hardcoded
(it's highly doubtful that anyone would).
Signed-off-by: Keir Fraser <keir@xensource.com>
Do it earlier on x86/64, properly free non-superpages on x86/32, and
leave a mapping of the boot trampoline (0x90000-0xA0000) in place.
Signed-off-by: Keir Fraser <keir@xensource.com>
handling.
1. Do not copy all VMCB register state in cpu_user_regs on every
vmexit.
2. Save/restore RAX inside asm stub (in particular, before STGI on
vmexit).
3. Simplify store/load_cpu_guest_regs() hook functions to synchronise
precisely the same state as VMX.
By my measurements this reduces the round-trip latency for a null
hypercall by around 150 cycles. This is about 3% of the ~5000-cycle
total on my AMD X2 system. Not a great win, but a nice extra on top of
the code rationalisation.
1. Remove erroneous modification to e820.c
2. Make sure Xen is relocated as high as possible below 4GB.
Signed-off-by: Keir Fraser <keir@xensource.com>
1. x86/64 Xen now relocates itself to physical high memory. This is
useful if we have devices that need very low memory, or if in
future we want to grant a 1:1 mapping of low physical memory to a
special 'native client domain'.
2. We now only map low 16MB RAM statically. All other RAM is mapped
dynamically within the constraints of the e820 map. It is
recommended never to map MMIO regions, and this change means that
Xen now obeys this constraint.
3. The CPU bootup trampoline is now permanently installed at
0x90000. This is necessary prereq for CPU hotplug.
4. Start-of-day asm is generally cleaned up and diff between x86/32
and x86/64 is reduced.
Signed-off-by: Keir Fraser <keir@xensource.com>
kfraser@localhost.localdomain
Simon Horman
Ian Campbell
Tom Wilkie
Steven Hand
Keir Fraser
Christian Limpach