Commit Graph
51 Commits
Author SHA1 Message Date
Stefano Stabellini 6e7f7a0c16 xen/x86/pvh: handle ACPI RSDT table in PVH Dom0 build
Xen always generates an XSDT table even if the firmware only provided an
RSDT table.  Copy the RSDT header from the firmware table, adjusting the
signature, for the XSDT table when not provided by the firmware.

This is necessary to run Xen on QEMU.

Fixes: 1d74282c45 ('x86: setup PVHv2 Dom0 ACPI tables')
Suggested-by: Roger Pau Monné <roger.pau@citrix.com>
Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Signed-off-by: Daniel P. Smith <dpsmith@apertussolutions.com>
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
2024-09-12 09:18:25 +02:00
Stefano Stabellini aa80a04df4 automation: restore CR filtering
After commit c36efb7fce ("automation: use expect to run QEMU") we lost
the \r filtering introduced by b576497e3b ("automation: remove CR
characters from serial output"). This patch reintroduced it.

Fixes: c36efb7fce ("automation: use expect to run QEMU")
Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
2024-08-22 13:07:39 -07:00
Stefano Stabellini 1e2a5f991f automation: add default QEMU_TIMEOUT value if not already set
The expectation is that QEMU_TIMEOUT should be set as a Gitlab CI/CD
variable but if not we should be able to run the pipeline anyway.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
2024-08-16 16:50:19 -07:00
Stefano Stabellini c36efb7fce automation: use expect to run QEMU
Use expect to invoke QEMU so that we can terminate the test as soon as
we get the right string in the output instead of waiting until the
final timeout.

For timeout, instead of an hardcoding the value, use a Gitlab CI
variable "QEMU_TIMEOUT" that can be changed depending on the latest
status of the Gitlab CI runners.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
2024-08-13 16:05:05 -07:00
Stefano Stabellini 98a462f8b1 automation: add "expect" to containers used to run QEMU tests
It will be used for QEMU tests.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
2024-08-12 15:20:30 -07:00
Stefano Stabellini 1c24bca387 automation: disable Yocto jobs
The Yocto jobs take a long time to run. We are changing Gitlab ARM64
runners and the new runners might not be able to finish the Yocto jobs
in a reasonable time.

For now, disable the Yocto jobs by turning them into "manual" trigger
(they need to be manually executed.)

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
2024-08-12 15:20:16 -07:00
Stefano Stabellini 449caecbdf automation: fix eclair gitlab jobs for merge requests
The "eclair" script calls action_push.sh even for merge request, while
instead action_pull_request.sh should be called, resulting in a job
failure with this error:

Unexpected event pull_request

Fix the script to call action_pull_request.sh appropriately.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Simone Ballarin <simone.ballarin@bugseng.com>
2024-08-06 12:29:05 -07:00
Stefano Stabellini 682ffdbda4 docs/misra: add R18.6 to rules.rst
In practice, we are already following R18.6 and we have zero violations
reported by ECLAIR (there are some cautions being reported.)

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Bertrand Marquis <bertrand.marquis@arm.com>
2024-07-30 15:14:31 -07:00
Stefano Stabellini afab29d088 public: s/int/int32_t
Straightforward int -> int32_t and unsigned int -> uint32_t replacements
in public headers. No ABI or semantic changes intended.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
2024-04-17 10:52:48 +01:00
Stefano Stabellini 856664f774 docs/misra/rules.rst: add rule 14.4
Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Bertrand Marquis <bertrand.marquis@arm.com>
2024-03-01 17:44:11 -08:00
Stefano Stabellini 4cac80e226 docs/misra/rules.rst: add rule 16.6 and 20.12
Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Julien Grall <jgrall@amazon.com>
2024-02-29 15:24:39 -08:00
Stefano Stabellini a60067f398 docs/misra/rules.rst: add Rule 16.2
Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Julien Grall <jgrall@amazon.com>
2023-12-15 13:09:22 -08:00
Stefano Stabellini f45e488e7b docs/misra/rules.rst: add more rules
Add the rules accepted in the last three MISRA C working group meetings.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
2023-12-11 11:27:20 +01:00
Stefano Stabellini 06e484767b docs/misra: add R11.1 R11.2 R11.3 R11.6
Add MISRA C Rules 11.1, 11.2, 11.3, 11.6 as discussed.

Explicitly add in the notes that conversions to integer types are
permitted if the destination type has enough bits to hold the entire
value. GCC gives enough guarantees in terms of preserving the bit
content in such situations.

Also allow for bool conversions (e.g. to check if a function point is
valid).

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
2023-11-15 16:01:55 -08:00
Stefano Stabellini 5704923f94 bitmap: fix nbits signess
To avoid potentially dangerous sign conversions in bitmap_switch, all
the callers of the bitmap_switch macro (which are all within bitmap.h)
should pass an unsigned int as first parameter.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
2023-11-07 12:38:50 -08:00
Stefano Stabellini 3d2d9e9022 SUPPORT: downgrade Physical CPU Hotplug to Experimental
The feature is not commonly used, and we don't have hardware to test it,
not in OSSTest, not in Gitlab, and not even ad-hoc manually by community
members. We could use QEMU to test it, but even that it is known not to
work on our end.

Also take the opportunity to rename the feature to "ACPI CPU Hotplug"
for clarity.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Release-acked-by: Henry Wang <Henry.Wang@arm.com>
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
2023-10-02 15:48:14 -07:00
Stefano Stabellini 5bdfcf7fe8 docs/misra: add rule 2.1 exceptions
During the discussions that led to the acceptance of Rule 2.1, we
decided on a few exceptions that were not properly recorded in
rules.rst. Add them now.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Bertrand Marquis <bertrand.marquis@arm.com>
Release-acked-by: Henry Wang <Henry.Wang@arm.com>
2023-09-29 11:00:47 -07:00
Stefano Stabellini 0b5bca91aa docs/misra: add rule 11.9
Following up from the MISRA C group discussion, add Rule 11.9 to
docs/misra/rules.rst.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Bertrand Marquis <bertrand.marquis@arm.com>
Release-acked-by: Henry Wang <Henry.Wang@arm.com>
2023-09-29 11:00:47 -07:00
Stefano Stabellini b1c84ab41a docs/misra: add 14.3
Add 14.3, with project-wide deviations.

Also take the opportunity to clarify that parameters of function pointer
types are expected to have names (Rule 8.2).

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Bertrand Marquis <bertrand.marquis@arm.com>
Release-acked-by: Henry Wang <Henry.Wang@arm.com>
2023-09-29 11:00:47 -07:00
Stefano Stabellini b5a601093d docs/misra: accept 11.7 and 11.8
As per the last MISRA C group discussion, let's accept 11.7 (for which
we have no violations) and 11.8.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
2023-09-14 18:45:38 -07:00
Stefano Stabellini 9a216e92de xen/arm: page: Handle cache flush of an element at the top of the address space
The region that needs to be cleaned/invalidated may be at the top
of the address space. This means that 'end' (i.e. 'p + size') will
be 0 and therefore nothing will be cleaned/invalidated as the check
in the loop will always be false.

On Arm64, we only support we only support up to 48-bit Virtual
address space. So this is not a concern there. However, for 32-bit,
the mapcache is using the last 2GB of the address space. Therefore
we may not clean/invalidate properly some pages. This could lead
to memory corruption or data leakage (the scrubbed value may
still sit in the cache when the guest could read directly the memory
and therefore read the old content).

Rework invalidate_dcache_va_range(), clean_dcache_va_range(),
clean_and_invalidate_dcache_va_range() to handle a cache flush
with an element at the top of the address space.

This is CVE-2023-34321 / XSA-437.

Reported-by: Julien Grall <jgrall@amazon.com>
Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Signed-off-by: Julien Grall <jgrall@amazon.com>
Acked-by: Bertrand Marquis <bertrand.marquis@arm.com>
2023-09-05 14:30:08 +02:00
Stefano Stabellini 1b7dc185f8 docs/misra: document gcc-specific behavior with shifting signed integers
Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
2023-08-30 18:59:52 -07:00
Stefano Stabellini 591fd09ffb docs/misra: add rules 10.1 10.2 10.3 10.4
10.1 with several caveats, described in the notes.
10.3 and 10.4 as "aspirational" guidelines, as clarified in the notes.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
2023-08-30 18:30:51 -07:00
Stefano Stabellini b0cd7499dd docs/misra: add exceptions to rules
During the discussions that led to the acceptance of the Rules, we
decided on a few exceptions that were not properly recorded in
rules.rst. Other times, the exceptions were decided later when it came
to enabling a rule in ECLAIR.

Either way, update rules.rst with appropriate notes.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
2023-08-23 12:46:24 -07:00
Stefano Stabellini 2763c33c6e automation: update jobs to use Debian Bookworm instead of unstable
Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
2023-08-14 14:42:16 -07:00
Stefano Stabellini 33a1c443d9 automation: update test-artifacts to use Debian Bookworm instead of unstable
Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
2023-08-14 14:42:03 -07:00
Stefano Stabellini 8ab05119df automation: switch from Debian unstable to bookworm
Debian unstable used in the Xen containers is actually bookworm.
Switching to bookworm which is now stable means we are not basing our
containers on a moving target anymore.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
2023-08-14 14:41:42 -07:00
Stefano Stabellini 6f9029cf8f automation: use Alpine 3.18 instead of 3.12 for all gitlab jobs
Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
2023-08-10 19:28:18 -07:00
Stefano Stabellini 1e7f896de2 automation: upgrade Alpine build and test artifact containers to 3.18
Alpine 3.12 is EOL. Also update the containerize script.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
2023-08-10 19:28:18 -07:00
Stefano Stabellini e55146071d automation: add missing "needs"
The test artifacts export jobs don't need prerequisites, so we should
specify "needs" with an empty array for them. That way, they are not
going to fruitlessly wait for previous jobs (ECLAIR jobs) to complete
before continuing.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
2023-08-04 14:35:16 -07:00
Stefano Stabellini 9a51409452 docs/misra: add Rule 1.1 and 5.6
Rule 1.1 is uncontroversial and we are already following it.

Rule 5.6 has been deemed a good rule to have by the MISRA C group.
However, we do have a significant amount of violations that will take
time to resolve and might require partial deviations in the form of
in-code comments or MISRA C scanners special configurations (ECLAIR).
For new code, we want this rule to generally apply hence the addition to
docs/misra/rules.rst.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
2023-07-24 15:31:24 -07:00
Stefano Stabellini 24909098fd docs/misra: add Rule 9.3
Specify that {} is allowed for zero-initialization.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
2023-07-12 13:02:07 -07:00
Stefano Stabellini 67f6063b1b docs/misra: add Rule 7.4 and 9.4
Rule 9.4 is non-controversial and we have no violations.

Rule 7.4 is considered a good idea with the caveat that assigning a
string literal to const void is allowed. I added a note to specify it.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
2023-07-11 13:14:12 -07:00
Stefano Stabellini 49ecef9fb4 docs/misra: add Rules 8.2, 8.3, 8.14
Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
2023-06-29 12:06:35 -07:00
Stefano Stabellini 314a54c1c2 xen/misra: add rules 1.4 and 2.1
Also add a comment at the top of the file to say rules.rst could be
changed.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
2023-06-19 12:18:31 -07:00
Stefano Stabellini d95f436c7d docs/misra: new rules addition
For Dir 1.1, a document describing all implementation-defined behaviour
(i.e. gcc-specific behavior) will be added to docs/misra, also including
implementation-specific (gcc-specific) appropriate types for bit-field
relevant to Rule 6.1.

Rule 21.21 is lacking an example on gitlab but the rule is
straightforward: we don't use stdlib at all in Xen.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
2023-06-19 12:17:38 -07:00
Stefano Stabellini 67fdffef92 automation: zen3 dom0pvh test
Add a PVH Dom0 test for the zen3 runner.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
2023-06-02 13:07:10 -07:00
Stefano Stabellini bdf48bf170 docs/misra: adds Mandatory rules
Add the Mandatory rules agreed by the MISRA C working group to
docs/misra/rules.rst.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
Tested-by: Luca Fancellu <luca.fancellu@arm.com>
2023-05-17 16:13:29 -07:00
Stefano Stabellini be6aa637db automation: add a Dom0 PVH test based on Qubes' runner
Straightforward Dom0 PVH test based on the existing basic Smoke test for
the Qubes runner.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
2023-05-15 14:46:36 -07:00
Stefano Stabellini 746774cd17 automation: introduce a dom0less test run on Xilinx hardware
The test prepares dom0 and domU binaries and boot artifacts, similarly
to the existing QEMU test. (TBD: share preparation steps with the
regular QEMU tests.)

However, instead of running the test inside QEMU as usual, it copies
the binaries to the tftp server root, triggers a Xilinx ZCU102 board
reboot, and connects to the real serial of the board.

Only run the job on protected branches with XILINX_JOBS set to true (the
"master" and "staging" on gitlab.com/xen-project/xen qualify).

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
2023-03-07 16:35:14 -08:00
Stefano Stabellini 3c55057bab automation: add Ubuntu container for Xilinx hardware tests
This container is only run on the controller PC (x86) to trigger the
test on a connected Xilinx ZCU102 physical board.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
2023-03-07 16:34:29 -08:00
Stefano Stabellini 6342f96689 automation: expand arm32 dom0 test adding xl domain creation
As part of the arm32 dom0 test, also create a simple domU using xl. To
do that, we need the toolstack installed in the dom0 rootfs. We switch
to using the kernel and rootfs built by the Yocto arm32 job.

Remove the PCI node from the host device tree: it is unused but causes a
Linux hang at boot.

Use xen-watchdog to trigger the domU creation for convience
(/etc/local.d is not handled by rootfs.)

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
2023-02-27 13:20:19 -08:00
Stefano Stabellini a0c3b87a76 automation: add binaries/ to artifacts for Yocto arm32 job
Copy the build output of Yocto builds to binaries/ for the arm32 target,
and export binaries/ among the jobs artifacts so that they can be reused
by other jobs.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
2023-02-27 13:19:31 -08:00
Stefano Stabellini adfb590ec3 automation: move yocto jobs to build stage
We are going to use artifacts produced by the Yocto builds in test jobs.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
2023-02-27 13:19:10 -08:00
Stefano Stabellini 4a1bceded2 Add more rules to docs/misra/rules.rst
As agreed during the last MISRA C discussion, I am adding the following
MISRA C rules: 7.1, 7.3, 18.3.

I am also adding 13.1 that was "agreed pending an analysis on the amount
of violations". There are zero violations reported by cppcheck.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
2023-02-02 12:01:10 -08:00
Stefano Stabellini d25aeb176e add SPDX to arch/arm/*.c
Add SPDX license information to all the *.c files under arch/arm.

The SPDX tags added by this patch were chosen based on the existing
copyright headers. When the copyright header was missing we used the
default license which is GPLv2 for Xen (as per the COPYING file).

One exception is domain_page.c which is a split from mm.c so the license
is GPLv2+.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Julien Grall <jgrall@amazon.com>
2022-12-09 14:55:33 -08:00
Stefano Stabellini 1527066a7e Introduce more MISRA C rules to docs/misra/rules.rst
Add the new MISRA C rules agreed by the MISRA C working group to
docs/misra/rules.rst.

Add a comment for Rule 19.1 to explain that Eclair's findings are
"caution" reports, not violations.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
2022-12-01 17:04:24 -08:00
Stefano Stabellini 17dfc79ce9 Add SPDX to CODING_STYLE
Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Julien Grall <jgrall@amazon.com>
Release-acked-by: Henry Wang <Henry.Wang@arm.com>
2022-11-11 12:19:18 -08:00
Stefano Stabellini 7b068ac890 Remove extra copies of licenses and license headers
Remove the extra copy of the GPL license and license copyright headers
from CONTRIBUTING and the top-level COPYING.

Mention of the LICENSES/ directory and also mention the SPDX tag.

SPDX support is still in progress and COPYING files in subdirectories
still need to be updated.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Julien Grall <jgrall@amazon.com>
Release-acked-by: Henry Wang <Henry.Wang@arm.com>
2022-11-11 12:19:15 -08:00
Stefano Stabellini 63ca22f920 Add licenses under LICENSES
Add the individual licenses under a new top-level directory named
"LICENSES". Each license file includes its related SPDX tags.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Acked-by: Julien Grall <jgrall@amazon.com>
Release-acked-by: Henry Wang <Henry.Wang@arm.com>
2022-11-11 12:18:01 -08:00
Stefano Stabellini 6d6aee437e automation: disable xen,enhanced in qemu-smoke-arm64
Disable xen,enhanced because we don't use PV drivers in this test and
also because the kernel used for testing is old and unpatched and would
break if xen,enhanced is passed.

This patch unbreaks gitlab-ci.

Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>
Reviewed-by: Ayan Kumar Halder <ayankuma@amd.com>
Tested-by: Ayan Kumar Halder <ayankuma@amd.com>
2022-08-05 17:44:59 +01:00