In 19284:0942BAA2A088 provision was made for running vnc and sdl
simultaneously. However, arrangements for saving and restoring the
new structure-configuration, and arrangements for allowing the new
code to load old savefiles, were not made.
This patch adds these facilities. Amongst other things, HVM VNC
save/restore will now work properly again.
Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com>
When the guest(pv-on-hvm guest that cannot suspend) reboot in
LiveMigration, the disconnecting of src-side is not transmitted to
dist-side. As a result, the error processing on the dist side is not
executed.
Signed-off-by: Tomonari Horikoshi <t.horikoshi@jp.fujitsu.com>
The suspend event channel functions are arch independent code
which xc_save uses.
The changeset of 19382:a5f497f02e34 cause link error on ia64.
This patch moves the functions into arch common file from
x86 specific file xc_domain_save.c
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Those patches based on AMD and SUN's MCA related jobs.
We have latest rebase after SUN's latest improvements.
We will have late following patches for recovery actions. This is a
basic framework for Intel.
Some implementation notes:
1) When error happens, if the error is fatal (pcc = 1) or can't be
recovered (pcc = 0, yet no good recovery methods),
for avoiding losing logs in DOM0, we will reset machine
immediately. Most of MCA MSRs are sticky. After reboot,
MCA polling mechanism will send vIRQ to DOM0 for logging.
2) When MCE# happens, all CPUs enter MCA context. The first CPU who
read&clear the error MSR bank will be this
MCE# owner. Necessary locks/synchronization will help to judge the
owner and select most severe error.
3) For convenience, we will select the most offending CPU to do most
of processing&recovery job.
4) MCE# happens, we will do three jobs:
a. Send vIRQ to DOM0 for logging
b. Send vMCE# to Impacted Guest (Currently Only inject to impacted
DOM0)
c. Guest vMCE MSR virtualization
5) Some further improvement/adds for newer CPUs might be done later
a) Connection with recovery actions (cpu/memory online/offline)
b) More software-recovery identification in severity_scan
c) More refines and tests for HVM might be done when needed.
This patch Enable basic MCA support For Intel
Signed-off-by: Jiang, Yunhong<yunhong.jiang@intel.com>
Signed-off-by: Ke, Liping <Liping.ke@intel.com>
The HPET broadcast was default not enabled because the old code use
HPET channel 0 in legacy replacing mode which will hide both PIT & RTC
irqs and cause issues if RTC is needed in some cases. The upstream
default broadcast timer is PIT, which is in periodic mode (100HZ) and
would be expensive to be used as oneshot. MSI capable HPET is coming
into being. It is capable to deliver interrupt through FSB directly,
and has no side effect.
This patch extends support for MSI HPET based on original legacy HPET
code. The broadcast timer selection logic becomes: 1. if MSI capable HPET
available, use multiple HPET channels (no more than possible cpu num)
in MSI mode; 2. else if legacy replacing mode available for HPET &
'hpetbroadcast' option is given in cmd line, use HPET channel 0 in
legacy mode; 3 else use PIT.
While entering broadcast, it gets a hpet channel (look for a spare one
first, if failing allocate a shared one), attach to current cpu, setup
the irq affinity & broadcast cpumask. While exiting broadcast, it
detach the used hpet channel and try to change the owner if the
broadcast mask is not empty. Some optimizations(static affinity) were
done for (MSI HPET channels >= possible cpu num) case.
A new hw_interrupt_controller 'HPET_MSI' is created for HPET MSI
interrupt handling.
Signed-off-by: Wei Gang <gang.wei@intel.com>=
Currently a slot may be specified for a hot-plug device,
but not for a pass-through device that is inserted at boot time.
This patch adds support for the latter.
The syntax is:
BUS:DEV.FUNC[@VSLOT]
e.g: 0000:00:1d:0@7
This may be important as recent changes that allow any free PCI
slot to be used for pass-through (and hotplug) may case pass-through
devices to be assigned in different locations to before. Amongst
other things, specifying the slot will allow users to move them
back, if there is a need.
Signed-off-by: Simon Horman <horms@verge.net.au>
On some platforms that support Queued Invalidation and Interrupt
Remapping, Dom0 S3 doesn't work. The patch fixes the issue.
1) In device_power_down(), we should invoke iommu_suspend() after
ioapic_suspend(); in device_power_up(), we should invoke
iommu_resume() before ioapic_resume().
2) Add 2 functions: disable_qinval() and disable_intremap(); in
iommu_suspend(), we invoke them and iommu_disable_translation().
Rename qinval_setup() to enable_qinval() and rename
intremap_setup() to enable_intremap().
3) In iommu_resume(), remove the unnecessary
iommu_flush_{context, iotlb}_global() -- actually we mustn't do that
if Queued Invalidation was enabled before S3 because at this point of
S3 resume, Queued Invalidation hasn't been re-enabled.
4) Add a static global array ioapic_pin_to_intremap_index[] to
remember what intremap_index an ioapic pin uses -- during S3 resume,
ioapic_resume() re-writes all the ioapic RTEs, so we can use the array
to re-use the previously-allocated IRTE;
5) Some cleanups:
a) Change some failure handlings in enable_intremap() to panic().
b) Remove the unnecessary local variable iec_cap in
__iommu_flush_iec().
c) Add a dmar_writeq(iommu->reg, DMAR_IQT_REG, 0) in
enable_qinval().
Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
If Queued Invalidation is not supported or not enabled, we should not
enable Interrupt Remapping even if HW supports it, because Interrupt
Remapping needs Queued Invalidation to invalidate Interrupt Remapping
Cache.
Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
Current scheduler only care performance, thus always picks pCPU from
the most idle package. This knob provides another option to pick pCPU from
least idle package, for user who want performance power balance.
Signed-off-by: Yu Ke <ke.yu@intel.com>
Signed-off-by: Tian Kevin <kevin.tian@intel.com>
Calculate cpu actual average freq according to aperf and mperf MSR and
then deliver to libxc interface
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
by both ondemand gov and user program
Current __get_measured_perf read aperf and mperf MSR and then clear
them for the sake of ondemand governor. This solution block user
program to get aperf and mperf on their purpose. In this patch, it no
longer clear aperf and mperf MSR, so that it can be used by both
ondemand gov and user program.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
This bug causes some pages not to be properly freed by xen, hence
after a cycle of 50 save\restore we don't have enough spare memory to
start 2 VMs any more. This patch fixes the issue properly unmapping
all the pages needed by the shared ring.
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Port 0x80 is already passed-through. Writes to port 0x80 are
traditionally used as IO delay. Recent Linux kernel versions can be
configured to use port 0xed instead (CONFIG_IO_DELAY_0XED=3Dy).
Ubuntu 8.04 and later kernels are configured to use port 0xed.
In Linux IO delay is implemented by (in|out)[bwl]_p. From a first
glance at Linux it looks like the only relevant usage of delayed IO is
in drivers/video/console/vgacon.c. Affected is VGA console
initialization and font setup. Output / scrolling is not affected.
Signed-off-by: Thomas Friebel <thomas.friebel@amd.com>
PCIe Alternative Routing-ID Interpretation (ARI) ECN defines the Extended
Function -- a function whose function number is greater than 7 within an
ARI Device. Intel VT-d spec 1.2 section 8.3.2 specifies that the Extended
Function is under the scope of the same remapping unit as the traditional
function. The hypervisor needs to know if a function is Extended
Function so it can find proper DMAR for it.
And section 8.3.3 specifies that the SR-IOV Virtual Function is under the
scope of the same remapping unit as the Physical Function. The hypervisor
also needs to know if a function is the Virtual Function and which
Physical Function it's associated with for same reason.
Signed-off-by: Yu Zhao <yu.zhao@intel.com>
Fix a cpufreq userspace limitation bug, so that userspace freq can
return to correct freq when freq_limitation return to high value (like
ppc event)
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>=
The reason is that tsc stops and it causes the inaccuracy.
And later we can write some scripts based on this patch.
Signed-off-by: Guanqun Lu <guanqun.lu@intel.com>
When `opcontrol --shutdown' is called after xenoprof is used on Dom0,
the vpmu owner becomes PMU_OWNER_NONE. So it is possible to acquire
the owner as PMU_OWNER_HVM and to allocate vpmu->context twice. As a
result, the hypervisor panics because of double-alloc/free of
vpmu->context.
Signed-off-by: Kazuhiro Suzuki <kaz@jp.fujitsu.com>
Keir Fraser
Isaku Yamahata