Suravee Suthikulpanit 0d57d46c71 iommu/amd: Fix logic for clearing the IOMMU interrupt bits
The IOMMU interrupt bits in the IOMMU status registers are
"read-only, and write-1-to-clear (RW1C).  Therefore, the existing
logic which reads the register, set the bit, and then writing back
the values could accidentally clear certain bits if it has been set.

The correct logic would just be writing only the value which only
set the interrupt bits, and leave the rest to zeros.

This patch also, clean up #define masks as Jan has suggested.

Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>

With iommu_interrupt_handler() properly having got switched its readl()
from status to control register, the subsequent writel() needed to be
switched too (and the RW1C comment there was bogus).

Some of the cleanup went too far - undone.

Further, with iommu_interrupt_handler() now actually disabling the
interrupt sources, they also need to get re-enabled by the tasklet once
it finished processing the respective log. This also implies re-running
the tasklet so that log entries added between reading the log and re-
enabling the interrupt will get handled in a timely manner.

Finally, guest write emulation to the status register needs to be done
with the RW1C (and RO for all other bits) semantics in mind too.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Tim Deegan <tim@xen.org>
Acked-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
master commit: 2823a0c7df
master date: 2013-07-02 08:49:43 +0200
2013-07-11 15:09:49 +02:00
2013-02-28 11:50:27 +00:00
2011-01-08 11:07:18 +00:00
2013-04-23 18:44:20 +02:00
2009-06-16 11:11:59 +01:00
2011-03-10 18:11:20 +00:00

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http://www.xen.org/

What is Xen?
============

Xen is a Virtual Machine Monitor (VMM) originally developed by the
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is freely-distributable Open Source software, released under the GNU
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The 4.1 release offers excellent performance, hardware support and
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Python Runtime Libraries
========================

Xend (the Xen daemon) has the following runtime dependencies:

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Intel(R) Trusted Execution Technology Support
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