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https://github.com/xen-project/xen.git
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Ian Campbell
443701ef0c
As recommended in http://www.gnu.org/licenses/gpl-howto.en.html. This is the result of: $ git grep -El Mass\|Temple\|Franklin | xargs ./fsf.pl Where fsf.pl is: #!/usr/bin/perl -w -pi.bak -0777 my $repl = 'If not, see <http://www.gnu.org/licenses/>.'; my $br = qr/(?:\s*\n\s*(?:[\*\#]|\/\/|\.\\" )?\s*|\s+)/; my $inwt = qr/[Ii]f${br}not,${br}write${br}(?:to${br})?the${br}Free${br}Software${br}Foundation,(?:${br}Inc\.,)?/; my $mass = qr/675${br}Mass${br}Ave,?${br}Cambridge,?${br}MA${br}02139,?${br}USA,?\.?/; my $franklin = qr/51${br}Franklin${br}St(?:reet)?(?:,${br}| - )Fifth${br}Floor,?${br}Boston,?${br}MA,?${br}02110-1301,?${br}USA,?\.?/; my $temple = qr/59${br}Temple${br}Place(?:,${br}| - )Suite${br}330,?${br}Boston,?${br}MA,?${br}021110?-1307,?${br}USA,?\.?/; s|$inwt$br$mass|$repl|m; s|$inwt$br$franklin|$repl|m; s|$inwt$br$temple|$repl|m; The only remaining mentions of these addresses are in COPYING files which I haven't touched. Some of the changed files are imports from elsewhere, however filtering them out is tricky, I think it is tolerable to have these files be modified here and then perhaps reverted on the next sync, since it's only 1-2 lines and obvious what is going on. Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
146 lines
8.1 KiB
C
146 lines
8.1 KiB
C
/*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation;
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* version 2.1 of the License.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __LIBXC_CPUFEATURE_H
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#define __LIBXC_CPUFEATURE_H
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/* Intel-defined CPU features, CPUID level 0x00000001 (edx) */
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#define X86_FEATURE_FPU 0 /* Onboard FPU */
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#define X86_FEATURE_VME 1 /* Virtual Mode Extensions */
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#define X86_FEATURE_DE 2 /* Debugging Extensions */
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#define X86_FEATURE_PSE 3 /* Page Size Extensions */
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#define X86_FEATURE_TSC 4 /* Time Stamp Counter */
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#define X86_FEATURE_MSR 5 /* Model-Specific Registers, RDMSR, WRMSR */
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#define X86_FEATURE_PAE 6 /* Physical Address Extensions */
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#define X86_FEATURE_MCE 7 /* Machine Check Architecture */
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#define X86_FEATURE_CX8 8 /* CMPXCHG8 instruction */
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#define X86_FEATURE_APIC 9 /* Onboard APIC */
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#define X86_FEATURE_SEP 11 /* SYSENTER/SYSEXIT */
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#define X86_FEATURE_MTRR 12 /* Memory Type Range Registers */
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#define X86_FEATURE_PGE 13 /* Page Global Enable */
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#define X86_FEATURE_MCA 14 /* Machine Check Architecture */
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#define X86_FEATURE_CMOV 15 /* CMOV instruction */
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#define X86_FEATURE_PAT 16 /* Page Attribute Table */
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#define X86_FEATURE_PSE36 17 /* 36-bit PSEs */
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#define X86_FEATURE_PN 18 /* Processor serial number */
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#define X86_FEATURE_CLFLSH 19 /* Supports the CLFLUSH instruction */
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#define X86_FEATURE_DS 21 /* Debug Store */
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#define X86_FEATURE_ACPI 22 /* ACPI via MSR */
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#define X86_FEATURE_MMX 23 /* Multimedia Extensions */
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#define X86_FEATURE_FXSR 24 /* FXSAVE and FXRSTOR instructions */
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#define X86_FEATURE_XMM 25 /* Streaming SIMD Extensions */
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#define X86_FEATURE_XMM2 26 /* Streaming SIMD Extensions-2 */
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#define X86_FEATURE_SELFSNOOP 27 /* CPU self snoop */
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#define X86_FEATURE_HT 28 /* Hyper-Threading */
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#define X86_FEATURE_ACC 29 /* Automatic clock control */
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#define X86_FEATURE_IA64 30 /* IA-64 processor */
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#define X86_FEATURE_PBE 31 /* Pending Break Enable */
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/* AMD-defined CPU features, CPUID level 0x80000001 */
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/* Don't duplicate feature flags which are redundant with Intel! */
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#define X86_FEATURE_SYSCALL 11 /* SYSCALL/SYSRET */
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#define X86_FEATURE_MP 19 /* MP Capable. */
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#define X86_FEATURE_NX 20 /* Execute Disable */
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#define X86_FEATURE_MMXEXT 22 /* AMD MMX extensions */
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#define X86_FEATURE_FFXSR 25 /* FFXSR instruction optimizations */
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#define X86_FEATURE_PAGE1GB 26 /* 1Gb large page support */
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#define X86_FEATURE_RDTSCP 27 /* RDTSCP */
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#define X86_FEATURE_LM 29 /* Long Mode (x86-64) */
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#define X86_FEATURE_3DNOWEXT 30 /* AMD 3DNow! extensions */
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#define X86_FEATURE_3DNOW 31 /* 3DNow! */
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx) */
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#define X86_FEATURE_XMM3 0 /* Streaming SIMD Extensions-3 */
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#define X86_FEATURE_PCLMULQDQ 1 /* Carry-less multiplication */
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#define X86_FEATURE_DTES64 2 /* 64-bit Debug Store */
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#define X86_FEATURE_MWAIT 3 /* Monitor/Mwait support */
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#define X86_FEATURE_DSCPL 4 /* CPL Qualified Debug Store */
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#define X86_FEATURE_VMXE 5 /* Virtual Machine Extensions */
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#define X86_FEATURE_SMXE 6 /* Safer Mode Extensions */
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#define X86_FEATURE_EST 7 /* Enhanced SpeedStep */
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#define X86_FEATURE_TM2 8 /* Thermal Monitor 2 */
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#define X86_FEATURE_SSSE3 9 /* Supplemental Streaming SIMD Exts-3 */
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#define X86_FEATURE_CID 10 /* Context ID */
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#define X86_FEATURE_FMA 12 /* Fused Multiply Add */
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#define X86_FEATURE_CX16 13 /* CMPXCHG16B */
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#define X86_FEATURE_XTPR 14 /* Send Task Priority Messages */
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#define X86_FEATURE_PDCM 15 /* Perf/Debug Capability MSR */
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#define X86_FEATURE_PCID 17 /* Process Context ID */
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#define X86_FEATURE_DCA 18 /* Direct Cache Access */
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#define X86_FEATURE_SSE4_1 19 /* Streaming SIMD Extensions 4.1 */
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#define X86_FEATURE_SSE4_2 20 /* Streaming SIMD Extensions 4.2 */
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#define X86_FEATURE_X2APIC 21 /* x2APIC */
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#define X86_FEATURE_MOVBE 22 /* movbe instruction */
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#define X86_FEATURE_POPCNT 23 /* POPCNT instruction */
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#define X86_FEATURE_TSC_DEADLINE 24 /* "tdt" TSC Deadline Timer */
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#define X86_FEATURE_AES 25 /* AES acceleration instructions */
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#define X86_FEATURE_XSAVE 26 /* XSAVE/XRSTOR/XSETBV/XGETBV */
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#define X86_FEATURE_AVX 28 /* Advanced Vector Extensions */
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#define X86_FEATURE_F16C 29 /* Half-precision convert instruction */
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#define X86_FEATURE_RDRAND 30 /* Digital Random Number Generator */
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#define X86_FEATURE_HYPERVISOR 31 /* Running under some hypervisor */
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/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001 */
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#define X86_FEATURE_XSTORE 2 /* on-CPU RNG present (xstore insn) */
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#define X86_FEATURE_XSTORE_EN 3 /* on-CPU RNG enabled */
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#define X86_FEATURE_XCRYPT 6 /* on-CPU crypto (xcrypt insn) */
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#define X86_FEATURE_XCRYPT_EN 7 /* on-CPU crypto enabled */
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#define X86_FEATURE_ACE2 8 /* Advanced Cryptography Engine v2 */
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#define X86_FEATURE_ACE2_EN 9 /* ACE v2 enabled */
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#define X86_FEATURE_PHE 10 /* PadLock Hash Engine */
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#define X86_FEATURE_PHE_EN 11 /* PHE enabled */
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#define X86_FEATURE_PMM 12 /* PadLock Montgomery Multiplier */
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#define X86_FEATURE_PMM_EN 13 /* PMM enabled */
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/* More extended AMD flags: CPUID level 0x80000001, ecx */
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#define X86_FEATURE_LAHF_LM 0 /* LAHF/SAHF in long mode */
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#define X86_FEATURE_CMP_LEGACY 1 /* If yes HyperThreading not valid */
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#define X86_FEATURE_SVM 2 /* Secure virtual machine */
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#define X86_FEATURE_EXTAPIC 3 /* Extended APIC space */
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#define X86_FEATURE_CR8_LEGACY 4 /* CR8 in 32-bit mode */
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#define X86_FEATURE_ABM 5 /* Advanced bit manipulation */
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#define X86_FEATURE_SSE4A 6 /* SSE-4A */
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#define X86_FEATURE_MISALIGNSSE 7 /* Misaligned SSE mode */
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#define X86_FEATURE_3DNOWPREFETCH 8 /* 3DNow prefetch instructions */
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#define X86_FEATURE_OSVW 9 /* OS Visible Workaround */
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#define X86_FEATURE_IBS 10 /* Instruction Based Sampling */
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#define X86_FEATURE_XOP 11 /* extended AVX instructions */
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#define X86_FEATURE_SKINIT 12 /* SKINIT/STGI instructions */
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#define X86_FEATURE_WDT 13 /* Watchdog timer */
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#define X86_FEATURE_LWP 15 /* Light Weight Profiling */
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#define X86_FEATURE_FMA4 16 /* 4 operands MAC instructions */
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#define X86_FEATURE_NODEID_MSR 19 /* NodeId MSR */
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#define X86_FEATURE_TBM 21 /* trailing bit manipulations */
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#define X86_FEATURE_TOPOEXT 22 /* topology extensions CPUID leafs */
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#define X86_FEATURE_DBEXT 26 /* data breakpoint extension */
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
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#define X86_FEATURE_FSGSBASE 0 /* {RD,WR}{FS,GS}BASE instructions */
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#define X86_FEATURE_TSC_ADJUST 1 /* Tsc thread offset */
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#define X86_FEATURE_BMI1 3 /* 1st group bit manipulation extensions */
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#define X86_FEATURE_HLE 4 /* Hardware Lock Elision */
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#define X86_FEATURE_AVX2 5 /* AVX2 instructions */
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#define X86_FEATURE_SMEP 7 /* Supervisor Mode Execution Protection */
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#define X86_FEATURE_BMI2 8 /* 2nd group bit manipulation extensions */
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#define X86_FEATURE_ERMS 9 /* Enhanced REP MOVSB/STOSB */
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#define X86_FEATURE_INVPCID 10 /* Invalidate Process Context ID */
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#define X86_FEATURE_RTM 11 /* Restricted Transactional Memory */
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#define X86_FEATURE_RDSEED 18 /* RDSEED instruction */
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#define X86_FEATURE_ADX 19 /* ADCX, ADOX instructions */
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#define X86_FEATURE_SMAP 20 /* Supervisor Mode Access Protection */
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#endif /* __LIBXC_CPUFEATURE_H */
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