Jan Beulich fc7f700cf1 x86emul: support AVX512_VP2INTERSECT insns ...

The standard memory access pattern once again should allow us to go
without a test harness addition beyond the EVEX Disp8-scaling one.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>

2020-07-21 14:00:25 +02:00

..

32

x86emul: also allow running the 32-bit harness on a 64-bit distro

2018-11-20 15:07:09 +01:00

blowfish.c

Replace FSF street address with canonical URL

2015-07-29 11:14:07 +01:00

evex-disp8.c

x86emul: support AVX512_VP2INTERSECT insns

2020-07-21 14:00:25 +02:00

Makefile

x86emul: also test decoding and mem access / write logic

2020-05-29 17:29:59 +02:00

opmask.S

x86emul: support AVX512{BW,DQ} mask move insns

2019-05-21 08:28:48 +02:00

predicates.c

x86emul: support ENQCMD insns

2020-05-29 17:32:55 +02:00

simd-aes.c

x86emul: add an AES/VAES test case to the harness

2019-07-17 15:44:54 +02:00

simd-clmul.c

x86emul: add a PCLMUL/VPCLMUL test case to the harness

2019-07-17 15:46:08 +02:00

simd-fma.c

x86emul: basic AVX512VL testing

2019-04-05 10:41:12 +02:00

simd-gf.c

x86emul: support GFNI insns

2019-07-17 15:43:06 +02:00

simd-sg.c

x86emul: support AVX512F scatter insns

2019-07-05 10:40:10 +02:00

simd-sha.c

x86emul: add a SHA test case to the harness

2019-07-17 15:45:34 +02:00

simd.c

x86emul: support remaining misc AVX512{F,BW} insns

2019-07-04 16:08:42 +02:00

simd.h

x86emul: add a PCLMUL/VPCLMUL test case to the harness

2019-07-17 15:46:08 +02:00

test_x86_emulator.c

x86emul: fix FXRSTOR test for most AMD CPUs

2020-07-06 18:12:22 +00:00

testcase.mk

x86/build: move -fno-asynchronous-unwind-tables into EMBEDDED_EXTRA_CFLAGS

2020-05-13 20:33:42 +01:00

wrappers.c

fuzz, test x86_emulator: disable sse before including always_inline fns

2018-09-25 16:30:32 +02:00

x86-emulate.c

x86emul: support FXSAVE/FXRSTOR

2020-05-29 17:35:09 +02:00

x86-emulate.h

x86emul: support AVX512_VP2INTERSECT insns

2020-07-21 14:00:25 +02:00