xen/riscv: fix switch_stack_and_jump() for range beyond 1M

The `j` instruction (JAL x0) used in switch_stack_and_jump() is a
J-type instruction with only a ±1MB range, and that this can
be exceeded in some configurations, causing a linker error:

  relocation truncated to fit: R_RISCV_JAL against `<symbol>'

Replace `j` with `jr` (JALR x0) via an explicit register, which has
unlimited range.

Found in a downstream branch when UBSAN instrumentation was enabled.

Note that the `tail` instruction looks more natural here, but `jr` is
chosen instead to avoid depending on how the assembler expands `tail`
and which scratch register it uses (`t1` in GAS), which would need to
be listed in the clobber section of `asm volatile`.

Fixes: e66003e7be ("xen/riscv: introduce setup_initial_pages")
Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
Reviewed-by: Baptiste Le Duc <baptiste.le-duc@vates.tech>
Acked-by: Jan Beulich <jbeulich@suse.com>

xen/arch/riscv/include/asm/current.h

@@ -54,7 +54,7 @@ DECLARE_PER_CPU(struct vcpu *, curr_vcpu);
 #define switch_stack_and_jump(stack, fn) do {               \
     asm volatile (                                          \
             "mv sp, %0\n"                                   \
-            "j " #fn :: "r" (stack), "X" (fn) : "memory" ); \
+            "jr %1" :: "r" (stack), "r" (fn) : "memory" );  \
     unreachable();                                          \
 } while ( false )