mirror of
https://github.com/xen-project/xen.git
synced 2026-10-28 02:01:24 +01:00
x86/spec-ctrl: Make svm_vmexit_spec_ctrl conditional
The logic was written this way out of an abundance of caution, but the reality is that AMD parts don't currently have the RAS-flushing side effect, nor do they intend to gain it. This removes one WRMSR from the VMExit path by default on Zen2 systems. Fixes:614cec7d79("x86/svm: VMEntry/Exit logic for MSR_SPEC_CTRL") Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> (cherry picked from commitc16a9eda77)
This commit is contained in:
1 parent
13e7c5a9f1
commit
3fbd85d087
1 file changed
+5
-5
@@ -114,15 +114,15 @@ __UNLIKELY_END(nsvm_hap)
|
||||
ALTERNATIVE "", DO_OVERWRITE_RSB, X86_FEATURE_SC_RSB_HVM
|
||||
|
||||
.macro svm_vmexit_spec_ctrl
|
||||
/*
|
||||
* Write to MSR_SPEC_CTRL unconditionally, for the RAS[:32]
|
||||
* flushing side effect.
|
||||
*/
|
||||
mov $MSR_SPEC_CTRL, %ecx
|
||||
movzbl CPUINFO_xen_spec_ctrl(%rsp), %eax
|
||||
movzbl CPUINFO_last_spec_ctrl(%rsp), %edx
|
||||
cmp %edx, %eax
|
||||
je 1f /* Skip write if value is correct. */
|
||||
mov $MSR_SPEC_CTRL, %ecx
|
||||
xor %edx, %edx
|
||||
wrmsr
|
||||
mov %al, CPUINFO_last_spec_ctrl(%rsp)
|
||||
1:
|
||||
.endm
|
||||
ALTERNATIVE "", svm_vmexit_spec_ctrl, X86_FEATURE_SC_MSR_HVM
|
||||
/* WARNING! `ret`, `call *`, `jmp *` not safe before this point. */
|
||||
|
||||