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x86/feature: Definitions for Indirect Branch Controls
Contemporary processors are gaining Indirect Branch Controls via microcode
updates. Intel are introducing one bit to indicate IBRS and IBPB support, and
a second bit for STIBP. AMD are introducing IBPB only, so enumerate it with a
separate bit.
Furthermore, depending on compiler and microcode availability, we may want to
run Xen with IBRS set, or clear.
To use these facilities, we synthesise separate IBRS and IBPB bits for
internal use. A lot of infrastructure is required before these features are
safe to offer to guests.
This is part of XSA-254.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>
master commit: 0d703a701c
master date: 2018-01-16 17:45:50 +0000
This commit is contained in:
Andrew Cooper authored and 
Jan Beulich committed
1 parent
6fef46d6fb
commit
602633eb73
7 files changed
+51
-4
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@@ -158,6 +158,8 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
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{"de", 0x00000001, NA, CPUID_REG_EDX, 2, 1},
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{"vme", 0x00000001, NA, CPUID_REG_EDX, 1, 1},
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{"fpu", 0x00000001, NA, CPUID_REG_EDX, 0, 1},
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{"ibrsb", 0x00000007, 0, CPUID_REG_EDX, 26, 1},
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{"stibp", 0x00000007, 0, CPUID_REG_EDX, 27, 1},
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{"topoext", 0x80000001, NA, CPUID_REG_ECX, 22, 1},
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{"tbm", 0x80000001, NA, CPUID_REG_ECX, 21, 1},
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{"nodeid", 0x80000001, NA, CPUID_REG_ECX, 19, 1},
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@@ -187,6 +189,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
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{"nx", 0x80000001, NA, CPUID_REG_EDX, 20, 1},
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{"syscall", 0x80000001, NA, CPUID_REG_EDX, 11, 1},
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{"procpkg", 0x00000004, 0, CPUID_REG_EAX, 26, 6},
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{"ibpb", 0x80000008, NA, CPUID_REG_EBX, 12, 1},
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{"apicidsize", 0x80000008, NA, CPUID_REG_ECX, 12, 4},
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{"nc", 0x80000008, NA, CPUID_REG_ECX, 0, 8},
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{"svm_npt", 0x8000000a, NA, CPUID_REG_EDX, 0, 1},
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+10
-2
@@ -144,7 +144,11 @@ static const char *str_e8b[32] =
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{
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[ 0] = "clzero",
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[1 ... 31] = "REZ",
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[1 ... 11] = "REZ",
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[12] = "ibpb",
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[13 ... 31] = "REZ",
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};
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static const char *str_7d0[32] =
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@@ -153,7 +157,11 @@ static const char *str_7d0[32] =
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[ 2] = "avx512_4vnniw", [ 3] = "avx512_4fmaps",
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[4 ... 31] = "REZ",
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[4 ... 25] = "REZ",
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[26] = "ibrsb", [27] = "stibp",
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[28 ... 31] = "REZ",
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};
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static struct {
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@@ -67,8 +67,25 @@ custom_param("bti", parse_bti);
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static void __init print_details(enum ind_thunk thunk)
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{
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unsigned int _7d0 = 0, e8b = 0, tmp;
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/* Collect diagnostics about available mitigations. */
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if ( boot_cpu_data.cpuid_level >= 7 )
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cpuid_count(7, 0, &tmp, &tmp, &tmp, &_7d0);
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if ( boot_cpu_data.extended_cpuid_level >= 0x80000008 )
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cpuid(0x80000008, &tmp, &e8b, &tmp, &tmp);
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printk(XENLOG_DEBUG "Speculative mitigation facilities:\n");
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/* Hardware features which pertain to speculative mitigations. */
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if ( (_7d0 & (cpufeat_mask(X86_FEATURE_IBRSB) |
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cpufeat_mask(X86_FEATURE_STIBP))) ||
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(e8b & cpufeat_mask(X86_FEATURE_IBPB)) )
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printk(XENLOG_DEBUG " Hardware features:%s%s%s\n",
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(_7d0 & cpufeat_mask(X86_FEATURE_IBRSB)) ? " IBRS/IBPB" : "",
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(_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP" : "",
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(e8b & cpufeat_mask(X86_FEATURE_IBPB)) ? " IBPB" : "");
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/* Compiled-in support which pertains to BTI mitigations. */
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if ( IS_ENABLED(CONFIG_INDIRECT_THUNK) )
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printk(XENLOG_DEBUG " Compiled-in support: INDIRECT_THUNK\n");
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@@ -27,3 +27,6 @@ XEN_CPUFEATURE(MSR_MISC_FEATURES, (FSCAPINTS+0)*32+13) /* MISC_FEATURES_ENABLES
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XEN_CPUFEATURE(LFENCE_DISPATCH, (FSCAPINTS+0)*32+14) /* lfence set as Dispatch Serialising */
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XEN_CPUFEATURE(IND_THUNK_LFENCE,(FSCAPINTS+0)*32+15) /* Use IND_THUNK_LFENCE */
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XEN_CPUFEATURE(IND_THUNK_JMP, (FSCAPINTS+0)*32+16) /* Use IND_THUNK_JMP */
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XEN_CPUFEATURE(XEN_IBPB, (FSCAPINTS+0)*32+17) /* IBRSB || IBPB */
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XEN_CPUFEATURE(XEN_IBRS_SET, (FSCAPINTS+0)*32+18) /* IBRSB && IRBS set in Xen */
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XEN_CPUFEATURE(XEN_IBRS_CLEAR, (FSCAPINTS+0)*32+19) /* IBRSB && IBRS clear in Xen */
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@@ -31,6 +31,14 @@
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#define EFER_LMSLE (1<<_EFER_LMSLE)
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#define EFER_FFXSE (1<<_EFER_FFXSE)
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/* Speculation Controls. */
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#define MSR_SPEC_CTRL 0x00000048
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#define SPEC_CTRL_IBRS (_AC(1, ULL) << 0)
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#define SPEC_CTRL_STIBP (_AC(1, ULL) << 1)
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#define MSR_PRED_CMD 0x00000049
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#define PRED_CMD_IBPB (_AC(1, ULL) << 0)
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/* Intel MSRs. Some also available on other CPUs */
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#define MSR_IA32_PERFCTR0 0x000000c1
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#define MSR_IA32_A_PERFCTR0 0x000004c1
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@@ -236,10 +236,13 @@ XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF Read Only interface */
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/* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */
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XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */
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XEN_CPUFEATURE(IBPB, 8*32+12) /* IBPB support only (no IBRS, used by AMD) */
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/* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
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XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */
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XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */
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XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */
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XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */
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XEN_CPUFEATURE(IBRSB, 9*32+26) /* IBRS and IBPB support (used by Intel) */
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XEN_CPUFEATURE(STIBP, 9*32+27) /* STIBP */
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#endif /* XEN_CPUFEATURE */
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@@ -256,6 +256,11 @@ def crunch_numbers(state):
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AVX512F: [AVX512DQ, AVX512IFMA, AVX512PF, AVX512ER, AVX512CD,
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AVX512BW, AVX512VL, AVX512VBMI, AVX512_4VNNIW,
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AVX512_4FMAPS, AVX512_VPOPCNTDQ],
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# Single Thread Indirect Branch Predictors enumerates a new bit in the
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# MSR enumerated by Indirect Branch Restricted Speculation/Indirect
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# Branch Prediction Barrier enumeration.
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IBRSB: [STIBP],
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}
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deep_features = tuple(sorted(deps.keys()))
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