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x86: drop cpu_has_sse{,2}
Commit dc88221c97 ("x86: rename XMM* features to SSE*") pointlessly
added them - these features are always available on 64-bit CPUs. (Let's
not assume this for MMX though in at least the insn emulator.)
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
This commit is contained in:
Jan Beulich committed
1 parent
7507ab8e7f
commit
62c6e94dba
2 files changed
+9
-6
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@@ -1326,6 +1326,11 @@ static bool vcpu_has(
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vcpu_must_have(feat); \
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})
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#else
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/*
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* For the test harness both are fine to be used interchangeably, i.e.
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* features known to always be available (e.g. SSE/SSE2) to (64-bit) Xen
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* may be checked for by just vcpu_must_have().
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*/
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#define host_and_vcpu_must_have(feat) vcpu_must_have(feat)
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#endif
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@@ -4910,9 +4915,9 @@ x86_emulate(
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if ( vex.opcx == vex_none )
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{
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if ( vex.pfx & VEX_PREFIX_DOUBLE_MASK )
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host_and_vcpu_must_have(sse2);
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vcpu_must_have(sse2);
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else
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host_and_vcpu_must_have(sse);
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vcpu_must_have(sse);
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ea.bytes = 16;
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SET_SSE_PREFIX(buf[0], vex.pfx);
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get_fpu(X86EMUL_FPU_xmm, &fic);
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@@ -5183,7 +5188,7 @@ x86_emulate(
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{
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case vex_66:
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case vex_f3:
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host_and_vcpu_must_have(sse2);
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vcpu_must_have(sse2);
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/* Converting movdqu to movdqa here: Our buffer is aligned. */
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buf[0] = 0x66;
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get_fpu(X86EMUL_FPU_xmm, &fic);
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@@ -5193,7 +5198,7 @@ x86_emulate(
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if ( b != 0xe7 )
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host_and_vcpu_must_have(mmx);
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else
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host_and_vcpu_must_have(sse);
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vcpu_must_have(sse);
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get_fpu(X86EMUL_FPU_mmx, &fic);
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ea.bytes = 8;
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break;
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@@ -38,8 +38,6 @@
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#define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
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#define cpu_has_mtrr 1
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#define cpu_has_mmx 1
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#define cpu_has_sse boot_cpu_has(X86_FEATURE_SSE)
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#define cpu_has_sse2 boot_cpu_has(X86_FEATURE_SSE2)
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#define cpu_has_sse3 boot_cpu_has(X86_FEATURE_SSE3)
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#define cpu_has_sse4_2 boot_cpu_has(X86_FEATURE_SSE4_2)
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#define cpu_has_htt boot_cpu_has(X86_FEATURE_HTT)
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