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x86/AMD: apply erratum 665 workaround
AMD F12h machines have an erratum which can cause DIV/IDIV to behave unpredictably. The workaround is to set MSRC001_1029[31] but sometimes there is no BIOS update containing that workaround so let's do it ourselves unconditionally. It is simple enough. [ Borislav: Wrote commit message. ] Signed-off-by: Emanuel Czirai <icanrealizeum@gmail.com> Signed-off-by: Borislav Petkov <bp@suse.de> [Linux commit: d1992996753132e2dafe955cccb2fb0714d3cfc4] Make applicable to Xen. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
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Emanuel Czirai authored and Jan Beulich committed
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@@ -661,6 +661,18 @@ static void init_amd(struct cpuinfo_x86 *c)
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smp_processor_id());
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wrmsrl(MSR_AMD64_LS_CFG, value | (1 << 15));
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}
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} else if (c->x86 == 0x12) {
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rdmsrl(MSR_AMD64_DE_CFG, value);
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if (!(value & (1U << 31))) {
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static bool warned;
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if (c == &boot_cpu_data || opt_cpu_info ||
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!test_and_set_bool(warned))
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printk(KERN_WARNING
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"CPU%u: Applying workaround for erratum 665\n",
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smp_processor_id());
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wrmsrl(MSR_AMD64_DE_CFG, value | (1U << 31));
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}
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}
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/* AMD CPUs do not support SYSENTER outside of legacy mode. */
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@@ -199,10 +199,11 @@
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/* AMD64 MSRs */
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#define MSR_AMD64_NB_CFG 0xc001001f
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#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46
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#define MSR_AMD64_LS_CFG 0xc0011020
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#define MSR_AMD64_IC_CFG 0xc0011021
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#define MSR_AMD64_DC_CFG 0xc0011022
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#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46
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#define MSR_AMD64_DE_CFG 0xc0011029
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#define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027
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#define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019
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