This patch is used to prepare exposing PCID/INVPCID features to hvm
guest.
The specific exposure result depend on hvm paging mode (hap/shadow),
which would be handled at next patch.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Committed-by: Keir Fraser <keir@xen.org>
Pushing stuff onto the stack on x86-64 when we do not specify
-mno-red-zone is unsafe. Since the complicated asm is due to register
pressure on i386, we simply implement an all-new simpler alternative
for x86-64.
Signed-off-by: Keir Fraser <keir@xen.org>
Acked-by: Jan Beulich <jbeulich@novell.com>
Provide pse36 cpuid bit if guest runs in 32bit PAE
or in long mode. Hyper-V refuses to start as
the "cpu does not provide required hw features"
if it does not find the pse36 cpuid bits.
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
Acked-by: Tim Deegan <tim@xen.org>
Committed-by: Tim Deegan <tim@xen.org>
In HVM domains the usable performance counters can be checked
automatically only, if cpuid leaf 0x0000000a is accessible.
Signed-off-by: Juergen Gross <juergen.gross@ts.fujitsu.com>
Committed-by: Ian Jackson <ian.jackson@eu.citrix.com>
Support TSC Rate MSR and enable TSC scaling for
nested virtualization.
With it, guest VMs don't need take #VMEXIT to calculate a translated
TSC value when it is running under TSC emulation mode.
I measured native performance of the rdtsc instruction
in the l2 guest with xen-on-xen and both host and
and l1 guest run under TSC emulation mode.
TSC scaling just needs MSR emulation and correct tsc offset
calculation to be done and thus can be emulated also on older
hardware. In this case rdtsc instruction is intercepted and
handled by the host directly and safes the cost of a full
VMRUN/VMEXIT emulation cycle.
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
The result of a CPUID Extended Topology Enumeration leaf for PV guests
is invalid as the level in ECX is ignored. This can cause some guests
to loop endlessly when trying to enumerate the topology.
Since the physical topology isn't useful to PV guests set the topology
leaf as unsupported.
Guests affected include Linux kernels prior 2.6.32 where a workaround
was applied ("xen: mask extended topology info in cpu",
82d6469916c6fcfa345636a49004c9d1753905d1).
Signed-off-by: David Vrabel <david.vrabel@citrix.com>
Write/read FS/GS base instructions enable user level code to
read/write FS & GS segment base registers for thread local storage.
Signed-off-by: Yang, Wei <wei.y.yang@intel.com>
This patch exposes ERMS feature to HVM and PV guests.
The REP MOVSB/STOSB instruction can enhance fast strings attempts to
move as much of the data with larger size load/stores as possible.
Signed-off-by: Yang, Wei <wei.y.yang@intel.com>
This patch exposes DRNG feature to HVM guests.
The RDRAND instruction can provide software with sequences of
random numbers generated from white noise.
Signed-off-by: Yang, Wei <wei.y.yang@intel.com>
Intel new CPU supports SMEP (Supervisor Mode Execution Protection). SMEP
prevents software operating with CPL < 3 (supervisor mode) from fetching
instructions from any linear address with a valid translation for which the U/S
flag (bit 2) is 1 in every paging-structure entry controlling the translation
for the linear address.
This patch adds SMEP support to HVM guest.
Signed-off-by: Yang Wei <wei.y.yang@intel.com>
Signed-off-by: Shan Haitao <haitao.shan@intel.com>
Signed-off-by: Li Xin <xin.li@intel.com>
Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
* Remove Linux-private defns with no direct relation to CPUID
* Remove word offsets into Linux-defined cpu_caps array
* Hard tabs -> soft tabs
Signed-off-by: Keir Fraser <keir@xen.org>
there are some new CPUID features that are safe for guests to see, as
they don't require OS awareness (FPU/ALU related instructions only).
Among features for new AMD CPUs there is also the PCLMULQDQ bit, which
Intel CPU have already for quite a while.
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
there are some new CPUID bits (and leaves) which Dom0 and PV domains
should not see to avoid trouble, since we don't emulate the features.
The most prominent one is a topology leaf, which contains information
specific to the physical CPU, not the virtual one. To avoid confusion
(and possibly crashes) due to a confused Dom0 scheduler simply disable
these bits.
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Keir Fraser <keir@xen.org>
In specific, it fixes the following issues:
1. The sub-leaves of CPUID:0x0000000D aren't contiguous. Hypervisor
shouldn't use register values to stop the enumeration. This patch
moves checking on XSAVE sub-leaves out of if-else statement. It also
bumps up sub-leaves to 63.
2. It creates a common function for xsave.
3. The main leaf 0 of CPUID:0x0000000D in current Xen is broken,
especially ECX and EBX registers. This patch cleans it up.
4. It adds support to detects EBX value of CPUID:0x0000000D main leaf
0 on-the-fly.
Signed-off-by: Wei Huang2 <wei.huang2@amd.com>
This patch would enable Xen to handle x2APIC MSR accessing of HVM
guest, which is faster(avoid decoding of MMIO accessing). The credit
comes to Gleb Natapov who complete the work for KVM.
Have tested with 4 vcpus guest, with/without x2apic support.
From: Sheng Yang <sheng.yang@intel.com>
Signed-off-by: Keir Fraser <keir@xen.org>
# User Ian Campbell <ian.campbell@citrix.com>
# Date 1282671421 -3600
# Node ID d1dd29a470ef1b9d2c77478a123326036dfe90bb
# Parent d7a4adad9c328decbd384d87b23001aea8951b86
tools/libxc, tools/libelf: Relicense under LGPL v2.1
Relicense these two libraries under LGPL v2.1 only except where
individual files already included the "or later" provision.
Copyright holders have been contacted by Stephen Spector and have all
agreed this change.
Removed tools/libxc/ia64/aclinux.h since it appeared to be
unused. There is a separate, more up to date, copy in
xen/include/acpi/platform/aclinux.h which does appear to be used.
Clarify the license of MiniOS privcmd.h under the same terms as other
tools/include/xen-sys headers.
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Stephen Spector <stephen.spector@citrix.com>
Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com>
This patch eliminate the global variables in libxenctrl (used for
logging and error reporting).
Instead the information which was in the global variables is now in a
new xc_interface* opaque structure, which xc_interface open returns
instead of the raw file descriptor; furthermore, logging is done via
xentoollog.
There are three new parameters to xc_interface_open to control the
logging, but existing callers can just pass "0" for all three to get
the old behaviour.
All libxc callers have been adjusted accordingly.
Also update QEMU_TAG for corresponding qemu change.
Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com>
- Put the guest rdtscp cpuid logic in xc_cpuid_x86.c.
- MSR_TSC_AUX's high 32bit is reserved, so only write the low 32bit.
Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
XSAVE/XRSTOR manages the existing and future processor extended states
on x86 architecture.
The XSAVE/XRSTOR infrastructure is defined in Intel SDMs:
http://www.intel.com/products/processor/manuals/
The patch uses the classical CR0.TS based algorithm to manage the
states on context switch. At present, we know 3 bits in the
XFEATURE_ENABLED_MASK: FPU, SSE and YMM. YMM is defined in Intel AVX
Programming Reference: http://software.intel.com/sites/avx/
Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
guests to use it (by setting cr4.OSXSAVE).
This prevents crashes in pvops kernels, as new versions of Linux
try to use this feature.
Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
Add a missing CPUID leaf that contains AMD-specific cache info.
Without this, Windows can spin trying to prefetch memory buffers using
a stride length of zero.
Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
Add pv guest support for the cpuid configuration and checking. That
feature only works for cpuid request which are coming from the guest's
kernel, a process could still call the cpuid directly.
A new policy for pv guest has been created in libxc. dom0 cpuid
emulation is left hardcoded in Xen.
Signed-off-by: Jean Guyader <jean.guyader@eu.citrix.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
Must save all 64 bits of RBX, not just the EBX sub-part.
Based on bug diagnosis and patch by Juergen Keil <jk@tools.de>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
- When we overwrite a cpuid's input, apply the default policy
for the other registers.
- For the python binding, get unsigned long instead long.
- Fix the multiple inputs cpuid's configuration parsing.
Signed-off-by: Jean Guyader <jean.guyader@eu.citrix.com>
CPUID's replies are now pre-calculated in libxc and given to the
hypervisor via a new domctl.
There are two parts to this feature:
- We can overwrite cpuid's replies.
- We can check that a vm is compatible with a host's processor.
Signed-off-by: Jean Guyader <jean.guyader@eu.citrix.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
Liu, Jinsong
Keir Fraser
Tim Deegan
Juergen Gross
Christoph Egger
David Vrabel
Yang, Wei
Tim Deegan
Wei Huang
cegger
Ian Campbell
Keir Fraser