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x86/IO-APIC: drop io_apic_get_unique_id()
Along the lines of what b89f8f054f ("x86/apic: Drop sync_Arb_IDs()")
said, the function is dead logic as well: All 64-bit capable Intel systems
have (at least) xAPIC (if not x2APIC).
As this removes the last user of APIC_XAPIC(), remove the macro as well.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Jason Andryuk <jason.andryuk@amd.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Release-Acked-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
This commit is contained in:
Jan Beulich committed
1 parent
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commit
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4 files changed
+1
-93
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@@ -19,7 +19,6 @@
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#define APIC_LVR_DIRECTED_EOI (1 << 24)
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#define GET_APIC_VERSION(x) ((x)&0xFF)
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#define GET_APIC_MAXLVT(x) (((x)>>16)&0xFF)
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#define APIC_XAPIC(x) ((x) >= 0x14)
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#define APIC_TASKPRI 0x80
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#define APIC_TPRI_MASK 0xFF
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#define APIC_ARBPRI 0x90
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@@ -184,7 +184,6 @@ extern bool skip_ioapic_setup;
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extern bool ioapic_ack_new;
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extern bool ioapic_ack_forced;
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extern int io_apic_get_unique_id (int ioapic, int apic_id);
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extern int io_apic_get_version (int ioapic);
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extern int io_apic_get_redir_entries (int ioapic);
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extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low);
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@@ -2092,86 +2092,6 @@ void ioapic_resume(void)
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spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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/* --------------------------------------------------------------------------
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ACPI-based IOAPIC Configuration
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-------------------------------------------------------------------------- */
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int __init io_apic_get_unique_id (int ioapic, int apic_id)
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{
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union IO_APIC_reg_00 reg_00;
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static physid_mask_t __initdata apic_id_map = PHYSID_MASK_NONE;
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unsigned long flags;
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int i = 0;
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const uint32_t broadcast_id = 0xf;
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/*
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* The P4 platform supports up to 256 APIC IDs on two separate APIC
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* buses (one for LAPICs, one for IOAPICs), where predecessors only
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* supports up to 16 on one shared APIC bus.
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*
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* TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
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* advantage of new APIC bus architecture.
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*/
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if (physids_empty(apic_id_map))
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apic_id_map = phys_cpu_present_map;
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spin_lock_irqsave(&ioapic_lock, flags);
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reg_00.raw = io_apic_read(ioapic, 0);
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spin_unlock_irqrestore(&ioapic_lock, flags);
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if (apic_id >= broadcast_id) {
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printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
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"%d\n", ioapic, apic_id, reg_00.bits.ID);
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apic_id = reg_00.bits.ID;
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}
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/*
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* Every APIC in a system must have a unique ID or we get lots of nice
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* 'stuck on smp_invalidate_needed IPI wait' messages.
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*/
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if ( physid_isset(apic_id, apic_id_map) )
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{
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for (i = 0; i < broadcast_id; i++) {
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if ( !physid_isset(i, apic_id_map) )
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break;
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}
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if (i == broadcast_id)
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panic("Max apic_id exceeded\n");
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printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
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"trying %d\n", ioapic, apic_id, i);
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apic_id = i;
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}
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physid_set(apic_id, apic_id_map);
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if (reg_00.bits.ID != apic_id) {
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reg_00.bits.ID = apic_id;
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spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_write(ioapic, 0, reg_00.raw);
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reg_00.raw = io_apic_read(ioapic, 0);
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spin_unlock_irqrestore(&ioapic_lock, flags);
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/* Sanity check */
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if (reg_00.bits.ID != apic_id) {
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printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
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return -1;
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}
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}
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apic_printk(APIC_VERBOSE, KERN_INFO
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"IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
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return apic_id;
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}
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int __init io_apic_get_version (int ioapic)
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{
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union IO_APIC_reg_01 reg_01;
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+1
-11
@@ -871,7 +871,6 @@ void __init mp_register_ioapic (
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u32 gsi_base)
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{
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int idx = 0;
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int tmpid;
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if (nr_ioapics >= MAX_IO_APICS) {
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printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
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@@ -891,16 +890,7 @@ void __init mp_register_ioapic (
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mp_ioapics[idx].mpc_apicaddr = address;
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set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
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if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
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&& !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
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tmpid = io_apic_get_unique_id(idx, id);
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else
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tmpid = id;
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if (tmpid == -1) {
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nr_ioapics--;
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return;
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}
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mp_ioapics[idx].mpc_apicid = tmpid;
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mp_ioapics[idx].mpc_apicid = id;
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mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
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/*
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